Fluke PM6690 Service Manual page 37

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Crossover Switch
This stage uses relays to direct the signal to the two compara-
tors. The following combinations are possible:
•
IN A to COMP A and IN B to COMP B
•
IN A to both COMP A and COMP B
•
IN B to both COMP A and COMP B
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Comparator
The comparator converts the analog signal to a binary logic
signal, with ECL levels (-0.9 V and –1.7 V). The trigger point
is set by a voltage from the trigger level circuitry. Tempera-
ture-compensated circuitry generates the voltages that control
the hysteresis of the comparator. A trimmer potentiometer ad-
justs the hysteresis window.
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Trigger Level Generation
Two 12-bit DACs in a single IC generate the two trigger levels
for Channel A resp. Channel B. A 2.5 V DC reference IC sup-
plies the reference voltage to the DACs. The DACs are con-
trolled by the processor over the SPI bus. The ±5 V dynamic
range at the BNC of the input amplifier is converted to ap-
proximately ±2.1 V at the comparator. This range must be
covered by the DAC. The voltage step from the DAC is ap-
proximately 1.2 mV, corresponding to 2.9 mV per step at the
BNC. Closed Case Calibration (CCC) is used for adjusting
the trigger levels. A known reference level is applied to the
BNC and the processor finds out the appropriate setting of the
DAC to match the reference level.
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Logic Level Conversion
The signals from the comparators must be converted from
ECL levels to LVPECL levels. There are three converter cir-
cuits. One for Channel A , one for Channel B and one for the
Set-Reset channel. The two main channels are fed to a Set-Re-
set flip-flop to make one-channel measurements with variable
hysteresis possible. There is also a converter for the signal
IMP ATT
A
B
IMP ATT
C OPTIONAL PRESCALER
Figure 4-8
Input amplifier block diagram.
AC/DC IMP
COUPL LIMITER CONV LP FILTER
-
+
-
+
AC/DC LIMITER IMP LP FILTER
CONV
COUPL
from an optional prescaler. It has PECL levels (+4.1 V and
+3.4 V) that are converted to LVTTL levels (+2.4 V and 0 V).
Oscillator Circuits
The processor has an 11.2896 MHz crystal. An internal PLL
in the processor uses the signal to make the internal processor
clock, approximately 50.8 MHz. The USB IC has a 6 MHz
crystal to make an internal clock and the GPIB IC has a 40
MHz crystal to make an internal clock.
The measurement reference oscillator (timebase) for the
timer/counter is a 10 MHz crystal oscillator or an optional
oven-controlled crystal oscillator (OCXO). Only one of these
is mounted. The user can also select an external reference sig-
nal, connected to the External Reference Input BNC on the
rear panel.
The standard oscillator consists of an inverter and a crystal.
The processor controls the frequency of the oscillator with a
PWM signal. The PWM signal is filtered to a DC level that
controls the capacitance of a capacitance diode. The varying
capacitance changes the frequency of the oscillator. The stan-
dard oscillator is adjusted with Closed Case Calibration. Ap-
ply a 10 MHz reference signal to Input A. The processor will
find the correct PWM signal to make the internal reference
frequency equal to the external reference frequency.
The optional oven-controlled oscillator is a complete oscilla-
tor in a small hermetic metal box. An internal accurate DC
voltage is available for use as a reference for a 12-bit DAC.
The filtered output voltage from the DAC sets the frequency
of the oven oscillator. The processor controls the DAC via the
SPI bus. The same Closed Case Calibration as for the stan-
dard oscillator is used. The oven oscillator is kept warm if the
line power is connected to the timer/counter, even if it is
switched off (in standby mode).
CROSSOVER
BUFFER
SWITCH
BUFFER
TRGLVL A
TRGLVL B
Hardware Functional Description 4-15
LVL SHIFT
ECL
LVPECL
ECL
S/R
FLIP-FLOP
LVPECL
ECL
LVPECL
LVL SHIFT
PECL
LVTTL