Fluke PM6690 Service Manual page 30

The 10 MHz reference signal is multiplied in a PLL to
100 MHz. The 100 MHz signal is used in the measuring logic
as a reference. The processor controls the PLL IC with the SPI
bus. A 100 MHz LC oscillator is used as the controlled ele-
ment where part of the C is a variable capacitance diode. Its
capacitance is controlled with a DC voltage from the PLL IC,
thus changing the frequency. The 10 MHz reference signal is
applied to the PLL IC as its reference and the 100 MHz output
frequency is exactly 10 times the reference frequency.
External Reference Input
A 1, 2, 5 or 10 MHz reference signal can be connected to the
rear panel BNC. After amplification in an operational ampli-
fier narrow pulses are made in two D flip-flops, one narrow
pulse for each input cycle. These pulses are fed to the 10 MHz
crystal filter. After the filter a reconstructed 10 MHz signal is
available. A variable capacitor is used for adjusting the filter.
Internal Reference Output
The selected 10 MHz reference signal (standard/oven oscilla-
tor or external reference) is available on the rear panel. The 10
MHz reference signal that is used internally by the dedicated
counter circuit (FPGA) logic is also sent to an output pin on
the FPGA. It is filtered to a sine wave and amplified in an out-
put buffer stage having 50 W drive capability.
Measuring Logic
The measuring logic consists of an FPGA, four interpolators
and an external control input on the rear panel. The FPGA
core uses +1.8 V supply voltage and the I/Os use +3.3 V sup-
ply voltage.
The FPGA is controlled by the processor over a 16-bit micro-
processor bus. Input signals (A, B, prescaler etc) and refer-
ence clock (internal 10 MHz oscillator or external reference)
are selected inside the FPGA. The logic for all measuring
functions and support functions (trigger indicators, start de-
lay, pacing etc) are inside the FPGA. A 100 MHz reference
clock is generated by a PLL circuit giving 10 ns basic mea-
surement resolution. To increase the measurement resolution
further, external interpolators are used. The measuring logic
also controls three LEDs on the display board; a GATE LED
indicating that a measurement is in progress, and two trigger
indicators telling that the comparators are triggering on the in-
put signals. A separate 32-bit bus is used for transferring mea-
surement data from the FPGA to the processor. Some control
signals to the hardware come from the FPGA due to a shortage
of processor pins.
The four external interpolators are identical. Depending on
the selected measurement function 0, 2, 3 or 4 interpolators
are used. A pulse representing the time from an event on the
input to the following rising edge of the 100 MHz reference is
fed to the interpolator. During the pulse time a constant cur-
rent is charging a capacitor. The voltage on the capacitor is
measured with a 10-bit ADC. The capacitor is discharged and
the interpolator is ready for a new measurement.
4-8 Hardware Functional Description
An external control input BNC is located on the rear panel. A
signal applied to this connector can be used for controlling the
start of a measurement, for instance. A comparator converts
the analog input signal to a logic signal.
Processor Circuits
The processor is a Triscend A7S. It contains an ARM7 core
and peripherals. It runs on a 30 MHz internal clock. The core
uses 2.5 V supply voltage and the I/Os use 3.3 V supply volt-
age.
A separate memory bus communicates with a 16-bit 8 MByte
flash memory and a 32-bit 32 MByte SDRAM. The flash
memory contains the program, data for loading the FPGA,
and stored data (calibration data etc.). At power-up the code is
copied from the flash to the SDRAM. It is run from the
SDRAM for faster execution.
The processor has a JTAG interface with a connector on the
circuit board.
A reset IC monitors the three main logic supply voltages, +3.3
V, +2.5 V and + 1.8 V. If a supply voltage fails, the processor
will be reset.
The regular 16-bit microprocessor bus is used for controlling
the FPGA, the GPIB interface and the USB interface. A sepa-
rate 32-bit bus is used for fetching measurement data from the
measuring logic.
Two other buses are also used, an SPI bus and an I
SPI bus is an output only bus and the processor controls the
100 MHz PLL, the trigger level DACs, and the DAC for the
optional oven oscillator. The I
for communication with the temperature measurement IC, the
display board (keyboard + LCD), the prescaler (optional), and
the relays and filters in the input amplifier.
The temperature reading over the I
trolling the fan speed. A PWM output is utilized. The signal is
filtered and the resulting DC voltage controls the fan.
Another PWM output is used for controlling the frequency of
the standard crystal oscillator.
The LCD controller is a peripheral inside the processor. This
controller sends signals and data to the driver circuits in the
LCD on the display board.
The processor also controls the OFF switch. Only a signal
from the processor can switch off the power. The OFF button
on the front panel is read by the processor. ON is handled
without the processor, since it cannot respond to external
stimulus in standby mode.
Power Supply
This timer/counter has no primary power switch. If connected
to line power there are live parts inside the cabinet, and some
supply voltages are present on the main circuit board, even if
2
C bus. The
2
C bus is bidirectional and used
2
C bus is used for con-