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Since both interfaces consist of only one IC each, trouble-
shooting is fairly simple. Check that the oscillator (40 MHz or
6 MHz) is running. Check that the processor communicates
with the selected IC. Make sure the external controller (GPIB
or USB) and the interconnection cable used are OK.
There is a separate bus for transfer of the measurement result
data from the FPGA to the processor. This bus is 32 bits wide
and has a clock of its own, FCLK (U11:101). A signal from
the processor, FEMPTY (X28), indicates to the FPGA that a
new packet of 8 words of 32 bits can be transferred. This is
done with the FWR signal (X30) together with the FCLK. The
FPGA can call for attention via an interrupt request signal,
FFIQ (X31). This is done when the FPGA would like to trans-
fer a packet to the processor. See Figure 6-41 for a typical tim-
ing diagram.
Another bus from the microprocessor is the SPI bus. It is a se-
rial bus with one data signal and one clock signal that are com-
mon for all ICs connected to the bus. A separate load signal
for each IC controls the loading of the data. Connected to the
SPI bus are (See Figure 6-42 to Figure 6-45):
•
The 100 MHz PLL IC (U9). The SPI bus is used only
for initialization after power on.
•
The optional oven oscillator IC (U5). The SPI bus is
used for initialization after power on and during a
timebase calibration.
•
The trigger levels IC (U46).
2
The last bus is the I
C bus. It is also a serial bus with two sig-
nals, SDA and SCL. Each connected IC has a unique address.
The message sent includes the address, and only the addressed
IC will listen to the message and respond by sending an ac-
knowledge to the master. Then it will react accordingly.
Introduction to the I
2
The I
C bus is a 2-line serial bus for the communication be-
tween the ICs. The microprocessor controls the communica-
tion by means of the clock line SCL. One or more slaves can
read or write on the data line SDA.
The SDA and SCL are high at standby. All ICs connected to
the bus can sink SDA to low as they are interconnected via
open collector outputs. The microprocessor starts and stops
the communication by sending terms of start and stop:
SDA
SCL
START
Figure 6-31
Terms of start and stop.
During transmission the SDA can be changed only when the
SCL is low.
The microprocessor always begins to send the address infor-
mation. The format of this address information is seven ad-
dress bits, one read/write bit, and one acknowledge bit.
6-22 Troubleshooting
2
C Bus
STOP
The addressed slave accepts by keeping the SDA line low
while the acknowledge bit (ACKN in ) is sent by the micro-
processor.
Example of addressing (address 30H):
SDA
SCL
1
1
1
2
3
4
START
MSB
Figure 6-32
Addressing.
The read/write bit R/W has the following meaning:
R/W = 1 means information from the slave to the µprocessor
R/W = 0 means information from the µprocessor to the slave.
The data information is sent after the address information.
The format of the data information is eight data bits followed
by one acknowledge bit. The reciever accepts by keeping the
SDA line low while the acknowledge bit (ACKN in ) is sent.
Example of data transmission (data 9BH):
SDA
SCL
1
2
3
4
1
1
MSB
Figure 6-33
Data transmission.
The processor is the Master on the I
are:
•
The digital I/O IC U40 with address 20hex. It controls
the loading of the FPGA at initialization after power on,
it controls the relays and filters in the input amplifiers,
and it reads the prescaler code at initialization after
power on.
•
The temperature measuring IC U39 with address
48hex.
•
The digital I/O IC U3 with address 21hex. It switches
the LCD display on after power-on initialization, it
scans the keyboard on the display circuit board.
The bus is connected to the prescaler connector J15 for future
use.
5
6
7
8
9
LSB
R/W
ACKN
5
6
7
8
9
LSB
ACKN
2
C bus. Slaves on the bus
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Troubleshooting
