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5
Sil9993CTG100 (MR MAIN BOARD ASSY : IC6881)
• HDCP Panel Link Receiver
Pin Arrangement (Top view)
Q13
51
Q12
52
Q11
53
Q10
54
Q9
55
OVCC
56
OGND
57
Q8
58
Q7
59
Q6
60
Q5
61
Q4
62
Q3
63
64
VCC
65
GND
OGND
66
OVCC
67
Q2
68
Q1
69
Q0
70
INT
71
RESET#
72
73
RSVDL
74
CSCL
75
CSDA
Block Diagram
72
RESET#
76
DSDA
I2C
SLAVE
77
DSCL
HDCP
KEYS
EEPROM
81
EXT_RES
83,84
RXC±
PANEL LINK
86,87
RX0±
TMDS
DIGITAL CORE
RX1±
91,92
RX2±
96,97
5
6
INT
71
REGISTERS
CONFIGURATION
LOGIC BLOCK
HDCP
DECRYPTION
ENGINE
XOR
MODE
MASK
CONTROL
TM
CONTROL SIGNALS
CONTROL SIGNALS
PDP-R05G
6
7
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2 DACGND
1
I2C
SLAVE
MCLK
AUX DATA
GEN
LOGIC
BOARD
AUDIO
DATA
DECODE
LOGIC
BOARD
VIDEO
COLOR
SPACE
CONVERTER
UP/DOWN
SAMPLING
36-39,42-44,48-55,
58-63,68-70
VIDEO
DAC
9
8
RSET
COMP
7
8
PLLOUT
PLLIN
PVCC2
PGND2
OVCC
RSVDO
RSVDO
RSVDL
VCC
GND
AnBPb
DACVCCB
DACGNDB
AnGY
DACVCCG
DACGNDG
RSET
COMP
AnRPr
DACVCCR
DACGNDR
N/C
N/C
DACVCC
75
CSDA
74
CSCL
26
MCLKOUT
27
MCLKIN
32
SCK
31
WS
30
SDO
29
SPDIF
35
DE
33
HSYNC
34
VSYNC
46
ODCK
Q[23-0]
12
AnGY
7
AnRPr
15
AnBPb
151
8
A
B
C
D
E
F
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