HP Visualize J2240 Service Handbook page 93

Table 4–7 SELFTESTS AND DIAGNOSTICS – Cache (cont.)
Ostat Code Name
FLT 2x71 DCACHE_RAM_D_ERR
FLT 2x72 DCACHE_RAM_TAG_ERR
Extended info
FLT 2xB0 DCACHE_PARITY
FLT 2xB1 DCACHE_EVEN_TAG_PARITY
FLT 2xB2 DCACHE__ODD_TAG_PARITY
FLT 2xB3 DCACHE_EVEN_TAG_PARITY
FLT 2xB4 DCACHE__ODD_TAG_PARITY
FLT 2xC3 ICACHE_WORD1_PARITY
x = Runway slot number
Table 4–8. PROCESSOR DEPENDENT HARDWARE (PDH)
Ostat Code Name
TEST 3x00 ROM_XSUM_TEST
TEST 3x01 PDH_CNTRL_TEST
TEST 3x02 SCR–SELFTEST
TEST 3x0B PDH_IO_CNTRL_TEST
TEST 3x1B CHECK_MODEL_STRING
TEST 3x1C TEST–SW–ID
TEST 3xBC TEST–SYSTEM–CLOCKS
TEST 3xCD CHECK–DEFAULTS
INIT 3x00 ROM_XSUM_INIT
INIT 3x01 PDH_CNTRL_INIT
INIT 3x02 SCR–INIT
INIT 3x07 INVOKE_LBD
INIT 3x0B PDH_IO_CNTRL_INIT
INIT 3x1C UPDATE_SW_ID
INIT 3xBC INIT–SYSTEM–CLOCKS
INIT 3xC4 CLEARING_EEPROM
INIT 3xCD INIT–DEFAULTS
INIT 3xD4 DEFAULTING_EEPROM2
WARN 3x03 SS_ERROR
4–42 Troubleshooting
Notes
Dcache RAM data error
Dcache RAM tag error
SAME AS 2x22
Dcache parity error
Icache word1 parity error
Notes
Start checksumming the FEPROM
Testing_PDH_CONTROL_REGISTER
Scratch RAM under test
Test PDH_IO_CNTRL_REG
Model string check
Check SW_ID
Test system clock setup
Cecking stable storage validity
FEPROM checksum correct
Init the PDH_CNTRL_REGISTER
Scratch RAM successfully initialized
Entering LBD
Init PDH_IO_CONTROL_REG
Perform SW_ID update
Done system clock check
Clearing and revalidating EEPROM
Initializing Stable Storage
(not on J280)
Error reading stable storage