Circuit Description - Yaesu FT-208R Maintenance Service Manual

TECHNICAL NOTES
The block diagram and circuit description to follow
will provide the owner with a better under­
standing of the FT-208R transceiver. Please refer
to the schematic diagram for details.
RECEIVER
The VHF signal from the antenna is fed through a
lowpass filter and antenna diode switch to RF
amplifier Q104
(2SC2549),
three-stage bandpass filter to minimize
modulation caused by strong out-of-band signals.
The amplified signal from Q 1 04 is fed to the first
mixer, Q 1 0 5
(2SC2786L),
mixed with the first IF signal delivered from the
PLL unit, producing a 1 6 .9 MHz first IF. The IF
signal is passed through a monolithic crystal filter,
XF 10 1 , which has a 3 dB bandwidth of ± 1 4 kHz,
and is fed to the second mixer,
Here the first IF signal is heterodyned with the
second local oscillator signal, 1 7.355 MHz (Model
A, D, E) or 1 6 .445 MHz (Model B, C), delivered
from Q10 7
(2SC2787L),
of 455 kHz. The I F signal is passed through a
ceramic filter, CF 10 1 , amplified by
then fed through another ceramic filter,
2787L),
CF 1 02 . The highly filtered IF signal is then fed to
Q109
which functions as an IF amplifier,
(MC33 57),
limiter, discriminator, and squelch control. The
amplification and limiting process eliminates ampli­
tude variations in the IF signal, which is then fed
to the discriminator section of Q 109 , where an
audio response is produced in accordance with a
corresponding frequency shift in the IF signal. The
audio signal is then amplified by Q 11 3
Q1 1 4
(2SA1175E), Qus (2SC2120Y),
The audio PA section delivers 500 mW
(2SA950Y).
of audio output power to the speaker.
When no carrier is present in the 4 5 5 kHz IF, the
high frequency noise at the output of the dis­
criminator is amplified by the noise amplifier
section of Q 109 . This amplified signal drives a
squelch switch in the same IC, which in turn biases
and
Q u8
(2SC2785E)
DC voltage is removed from AF amplifier
thus silencing the receiver.
C I R CU I T D E S C R I P T I O N
which is protected by a
inter­
where the RF signal is
Q 1 06 (2SC2787L).
resulting in a second IF
Q 1 os (2SC-
(2SC2785E),
and
Q116
such that
Q 11 7 (2SA1175E)
Q 11 4
When a carrier is present in the 4 5 5 kHz I F , the
noise is removed from the discriminator output,
and Q 11 4 is then biased for normal operation, thus
allowing receiver recovery. VR102 sets the squelch
sensitivity level. Scanning control voltages are also
provided by Q 1 09 , allowing interactive operation
with the Central Processing Unit for control of the
SCAN STOP function.
TRANSMITTER
The transmitter produces a frequency modulated
signal. The audio input from the microphone or
DTMF encoder Q 304
Q2 17
(µPC577H),
amplitude of the audio input and filters out signal
components above the normal speech range. The
audio signal is then applied to varactor diode D209
which varies the frequency of a 1 6 .9 MHz
(FC53 ),
crystal oscillator, Q2 13
then delivered to the balanced mixer and amplifier
stages.
A portion of the output from VCO (Voltage
Controlled Oscillator) Q201
through buffer amplifier Q202
(Phase Locked Loop) mixer Q20 3
which is also supplied with a PLL local signal of
1 2 5 . 59 5 MHz (Model A, D, E) or 1 24 . 5 8 7 5 MHz
(Model B, C) delivered from Q209
This results in a 1 . 50 5 -5. 500 MHz (Model A, D ,
E ) o r 2 . 5 1 2 5 MHz-4.500 M H z (Model B ) , 2 . 5 1 2 5
MHz-6 . 500 MHz (Model C) PLL IF signal. See
page 2-4 for Frequency Relationships.
The PLL IF signal is amplified by Q204 and Q20 5
and then fed to
(2SC2786L)
This programmable divider divides the signal by a
factor of 30 1 - 1 1 00 (Model A, D , E), 20 1 -360
(Model B), 20 1 -520 (Model C), producing basic
5 kHz (Model A, D, E), 1 2. 5 kHz (Model B, C)
steps for the synthesizer. One section of
as a 5 . 7 6 MHz (Model
(Model B , C) oscillator, which, in tum, is divided
into 5 kHz ( 1 2 . 5 kHz) steps. The phase com­
,
parator section of
the PLL IF signal with that of the PLL reference
signal, and any difference in phase produces an
error-correcting voltage, which is used to control
varactor diodes to lock the PLL onto the correct
frequency . This feedback system produces a highly
stable output signal.
2-2
is amplified by
(MK5087)
which also limits the maximum
This signal is
(2SC2786L).
(2SK192Y)
(2SC2786L)
(2SC2786L),
(2SC2786L).
Q206 (µPD2819C).
Q206
A, D, E) or 7 . 2 MHz
then compares the phase of
Q206
is fed
to PLL
acts