Circuit Description - Yaesu FT-2500M Technical Supplement

Circuit Description

tuned to its peak level, preset by Center-Stop
trimmer VR2007.
Transmit Signal Path
Speech input from the microphone is deliv­
ered via the Mic (Jack) Unit and DISPLAY Unit to
the CNTL Unit, where it passed through Mic
Mute switch D2003 (DAP202K) for amplification
and pre-emphasis by Q2007-1 (NJM2902M-%) .
To prevent over-deviation, the audio is processed
by IDC (instantaneous deviation control) stage
Q2007-%, and then lowpass filtered by Q2007-%
-%(NJM2902M)
&
before delivery to the modula­
tor on the VCO Unit.
If a CTCSS tone is enabled for transmission,
the subaudible tone from microprocessor Q2006
on the CNTL Unit is lowpass filtered by Q2001-1
and mixed with the !DC-processed speech audio.
Also, DTMF tones generated by the FRC-6 op­
tion(if installed) or directly from the microproces­
sor, are applied to the transmit audio chain at the
input of the IDC stage. The microprocessor also
disables microphone at Mic Mute switch D2003.
The modulating audio is delivered to diode
D305 (18V214) on the VCO Unit, frequency
modulating the PLL carrier up to ± 5 kHz from
the unmodulated carrier at the transmitting fre­
quency. The modulated signal from transmitter
VCO Q303 (28C3356) is buffered by Q305
(2SC2759) and delivered to the Main Unit for
amplification by Q 1012 (28C2759), Q lO ll
(MMBR951 L) and Q1010 (2SC2053). The low
level transmit signal is then finally amplified by
PA module Q1009 (M67781 L) up to 50 watts.
Harmonic spurious radiation in the final output
is suppressed by a 3-pole lowpass filter on the
Main Unit, and the transmit signal then passes
through %-wave antenna switch D1016
before delivery to the antenna.
Automatic Transmit Power Control
RF power output from the final amplifier is
sampled by C 1064 and rectified by D1017
(18897). The resulting DC is passed by high/me­
dium/low power controller Q1017 (FM81) and
transmit inhibit gate Q1018 (IMX1) to Automatic
Power Controller Q1019 (28811438) which
regulates supply voltage to transmitter RF ampli­
fiers Q1009 and Ql010, so as to maintain stable
high, medium or low output power under vary­
ing antenna loading conditions.
1-8
Spurious Suppression
Generation of spurious products by the trans­
mitter is minimized by the fundamental carrier
frequency being equal to the final transmitting
frequency, modulated directly in the transmit
VCO. Additional harmonic suppression is pro­
vided by a 3-pole lowpass filter consisting of
Ll002, L1013, L1014 and C1002, C1061, C1063,
C1065-C1067, and Cl164, resulting in more than
60 dB harmonic suppression (for transmitting
frequencies in the amateur band) prior to deliv­
ery to the antenna.
PLL Frequency Synthesizer
PLL circuitry on the Main Unit consists of
prescaler Q1025 (MC120228LAD) and PLL sub­
system IC Q1024 (MC145158F2), which contains
a reference oscillator I divider, serial-to-parallel
data latch, programmable divider and a phase
comparator. Stability is obtained by a regulated
5-V supply to Q1024 and temperature compen­
sating capacitors associated with 12.8-MHz fre­
quency reference crystal X1002.
Receiver VCO Q301 (28C3356) on the VCO
Unit oscillates between 118.6 and 152.6 according
to the programmed receiving frequency. The
VCO output is buffered by Q305 (2SC2759) on
the VCO Unit, and then returned to the MAIN
Unit where a sample of the output is buffered by
Q1028 (28C2714Y) for application to prescaler /­
swallow counter Ql025. There the VCO signal is
divided by 64 or 65, according to a control signal
from the data latch section of Q1024, before being
applied to the programmable divider section of
the PLL chip.
The data latch section of Q1024 also receives
(UM9415)
serial dividing data from microprocessor Q2006
on the CNTL Unit, which causes the predivided
VCO signal to be further divided by 23,720 -
30,520 in the programmable divider section, de­
pending upon the desired receive frequency, so
as to produce a 5-kHz or 6.25-kHz derivative of
the current VCO frequency. Meanwhile, the refer­
ence divider section of Q1024 divides the 12.8-
MHz cry stal reference by 2560 (or 2048) to
produce the 5-kHz (or 6.25-kHz) loop reference
(respectively).
The 5-kHz (or 6.25-kHz) signal from the pro­
grammable divider (derived from the VCO) and
that derived from the crystal are applied to the
FT-2500M Technical Supplement