Circuit Description - Yaesu FT-101ZD Instruction Manual

The block diagram and following circuit descrip­
tion will provide you with a better underst anding
of the design of this transceiver. The circuit
description is tailored to the full-feature FT-
1 0 1 ZD, and the reader should note that the
counter unit and digital display are optional
features for the FT- 1 0 1 Z.
The FT- 1 0 1 ZD consists of a premix-type single
conversion sy st e m , using a 9 MHz IF for all m odes
o f operation.
RECEIVER
The RF input signal from the antenna is fed
through antenna relay RL 2 , lamp fuse FH2 ,
attenuator swit ch S2oo4 (lo cated on the LEVER
SW unit , PB- 1 9 7 5 ) , 9 MHz trap L2 1 o 1 and C 1 20 7
( located on the T RIMMER A UNIT) , and input
t ransformer T 1 to pin 3 of the RF UNIT .
T i

CIRCUIT DESCRIPTION

-
' 1
- - - - - -
:- ;- :;
- - - R R A - -
I 00 1
3SK51 · 03
T2 I
I
I
i�
I
I
I
I
I
� _!'��� - R� �N_!! � � l__ __l_
1 2 V
_ _
RF
UNIT (PB- 1 96 0)
The incoming signal is amplified by the RF
amplifier, Q 1 0 1
used in a grounded source configuration . This
transistor has superior immunity from intermodula­
tion distortion. The amplified signal is then fe d
through a source follower, Q 1 02
balanced mixer consisting o f
where the input signal is heterodyned
(2SK1 9GR ) ,
with the local oscillator signal . The lo cal signal is
delivered from buffer amplifier Q 1 0 7
and the resulting IF signal o f 8 . 9 8 7 5 MHz is fed
through T 1 0 2 to J 1 0 1 .
The input and output of the RF amplifier are
permeability-tuned circuits, resulting in high sensi­
tivity and e x cellent rej e ction of unwanted out-of­
band signals.
-
M-;:- - - R:-M-:- - -
- R F
;; �
- - - - - - - -
-
002
003
2SK19GR
J 3 1 0
ROS
1 00
- - - - - _ - - - -
-
- - - -
2 2
-
-
a dual-gate M OSFET
( 3 SK5 1 -03 ) ,
(J3 1 0 ) ,
Q 1 o 3
J
- - - - _ _ _
to the
and Q l o4
( 2N44 27 ) ,