Yaesu FT-208R Maintenance Service Manual page 28

The IF signal is fed to a balanced mixer, Q214 /Q21s
where the 1 6 .9 MHz FM signal is
(2SK193K),
mixed with a local signal from the VCO , with the
output being at the ultimate transmitting fre­
quency. A three-stage auto-tune resonator between
Q214/Q21s and Q216, along with a filter immediate­
ly following Q216
(2SC2786L),
rejection of spurious signals.
The signal is delivered to a three-stage RF power
amplifier consisting of Q101
and Q103
(2SC2053) ,
power butput of 2 . 5 watts.
HETERODYNE OSCILLATOR
The heterodyne signal of 1 27 . 1 00- 1 3 1 .09 5 MHz
(Model A, D, E),
(Model B ) , 1 27. 1 00 - 1 3 1 .0875 MHz (Model C)
for the receiver and transmitter is generated by the
PLL circuit just described.
The VCO, Q201
(2SK192Y) ,
at one of the above frequencies. The oscillator
frequency is controlled
which varies the capacitance of the
D201 (1 T25) ,
oscillator tuned circuit in accordance with a
control voltage. This control voltage is generated
by phase comparator Q206
and delivered through a lowpass filter
(µPD2819C)
consisting of Q2o?
(2SK184Y)
to the VCO.
2785E),
This voltage is then fed to varactor diode D201 ,
which changes the output phase of the VCO to
lock with that of the reference signal. The control
voltage is also used to tune the transmitter band­
pass filters and local signal amplifier filter, thus
providing optimum spurious attenuation .
PLL CONTROL SECTION
The PLL Control Unit employs a 4-bit micro­
processor chip,
Q301
provides various control information for display
control, transmit disable, DTMF encoder, etc. The
reader is referred to the block diagram of the PLL
control Unit for an explanation of the functions
of the CPU. A full description of each logic state
is beyond the scope of this manual.
provide superior
(2SC2512), Q102
resulting in a
(2SC2196),
1 27. 1 00 - 1 2 9 .0875 MHz
generates a signal
by varactor diode
as mentioned earlier,
,
and Q208
(2SC-
which
(HD44820A07) ,
2-3
TECHNICAL NOTES