Nvidia MSTFLINT Documentation page 77

Configure FEC:
mstlink -d <device> -p <port_number> --fec RS
Configure Port for Physical Test Mode:
mstlink -d <device> -p <port_number> --test_mode EN (--rx_prbs PRBS31 --rx_rate 25G --tx_prbs PRBS7 --tx_rate 10G
--invert_rx_polarity --invert_tx_polarity)
Perform PRBS Tuning:
mstlink -d <device> -p <port_number> --test_mode TU

RX and TX lane rates for new devices includes the PAM4 speeds (50G_1X and 100G_2X)
eg:
mstlink -d <device> --test_mode EN --rx_rate [normal speeds | 50G_1X |
100G_2X] --tx_rate [normal speeds | 50G_1X | 100G_2X]

The PRBS pattern that is configured in PAM4 rates is PRBSQ.
Cable operations:
mstlink -d <device> --cable [Options]
Dump cable EEPROM pages:
mstlink -d <device> --cable --dump
Get cable DDM info:
mstlink -d <device> --cable --ddm
Read from cable:
mstlink -d <device> --cable --read --page <page number> --offset <bytes offset> --length <number of bytes>
Write to cable:
mstlink -d <device> --cable --write <bytes separated by comma> --page <page number> --offset <bytes offset>
Configure Transmitter Parameters for 16nm devices:
mstlink -d <device> -p <port_number> --serdes_tx <pre_2_tap>,<pre_tap>,<main_tap>,<post_tap>,<ob_m2lp>,<ob_amp>
Configure Transmitter Parameters (on lane, to database):
mstlink -d <device> -p <port_number> --serdes_tx <polar-
ity>,<ob_tap0>,<ob_tap1>,<ob_tap2>,<ob_bias>,<ob_preemp_mode>,<ob_reg>,<ob_leva> (--serdes_tx_lane <lane number>)
(--database)
To start the margin scan with the default configuration (measure_time 600 sec per margin):
mstlink -d <device> --port_type PCIE --margin
To start the margin scan with specific time\lane:
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