Panasonic PT-56DLX25 Service Manual page 68

PT-56DLX75 / PT-61DLX75
VIDEO SIGNAL PATH I BLOCK DIAGRAM (2/2)
Y DATA (8BIT)
UV DATA (8BIT)
IC4265 (VIDEO SIGNAL PROCESS)
E1,E2,E4,
F1-F5,G2-G4
FIFO SDRAM
INTERFACE INTERFACE
G1,H1-H3,J1-J5,
K1-K5,L1,L5
L2 V-SYNC
H-SYNC
L3
L4 CLOCK(28.636MHz)
MAIN SIGNAL PATH
B1-B3,C1-C4,D2-D4
D1 V-SYNC
E5 H-SYNC FOR MAIN SIGNAL
E3 CLOCK
IP CONVERTER
SUB SIGNAL PATH
PICTURE CONTROL
MULTI WINDOW
A6,A7,B6,B7,
C5,C6,D5,E6 PICTURE IN PICTURE
A8,A9,B8,C7, SPLIT SCREEN
C8,C9,D7,D8
SEARCH
A5 V-SYNC SCALER(720p CONVERTER)
B5 H-SYNC FOR SUB SIGNAL
OSD MIX
B9 CLOCK
A2 HDMI CLOCK
FR CLOCK2(20.25MHz)
B4
MODE FREQUENCY
(480i)/
27MHz
480p
720p/
74.25MHz
1080i
INPUT MODE FREQUENCY
VIDEO 480i 28.636MHz
COMPONENT 480i 28.636MHz
480p 57.40MHz
720p 74.25MHz
1080i 74.25MHz
RGB VGA60 50.34MHz
SVGA60 40.00MHz
XGA60 65.00MHz
DIGITAL TUNER/SD CARD/OSD SIGNAL PATH
Y DATA (8BIT)
H23,H24,J24-J26,
K24-K26
UV DATA (8BIT)
E23-E25,F24-F26,
G25,G26
V-SYNC
D25
E26 H-SYNC
H25 CLOCK
G24 OSD V-SYNC
H26 OSD H-SYNC
D26 OSD CLOCK
D6,D11,ETC
L4272
VCC
L4273 D22,D23,ETC
VCC
P3,P4
L4277
AVD
D17,E17,ETC
L4278
AVD
R5
L4281
+3.3V AVD
IC4261
AE14
+1.8V
5 4 AVD
REG.
IC4262
C18,D18
+3.3V
+5V 5 4 VDDI
REG.
IC4259
E7,E8,ETC
+1.8V
+2.5V VCC
1 3
REG. GC4U
MAIN VIDEO SIGNAL
IC4264 (64M MEMORY)
<CLOCK(129MHz)>
Y22-Y25,AA23-AA26,AB18,AB19,AC22, DATA BUS(32BIT)
64M
AD17,AD18,AD21-AD24,AE17,AE18,
MEMORY
AE21-AE26,AF17,AF18,AF21-AF25
1,3,9,15,29,35,41,
43,49,55,75,81
VCC
<FOR SCALER(720p COVERTER)>
R DATA (8BIT)
A25,B24-B26,
C24-C26,D24
G DATA (8BIT)
V3,W1-W3,
W5,Y2,Y3,Y5
B DATA (8BIT)
V24-V26,W26,
Y1,AA1-AA3
H-SYNC
W24
V-SYNC W25
CLOCK(75.26MHz)
Y26
TO
H-SYNC
SYSTEM CONTROL
V-SYNC
BLOCK DIAGRAM
OSD-CLOCK OSD-CLOCK
L26
OSD H-SYNC OSD H-SYNC
L24
OSD H-SYNC M25 OSD H-SYNC
OSD V-SYNC M24 OSD V-SYNC
OSD-YM M23 OSD-YM
FROM/TO
OSD-YS N26 OSD-YS
SYSTEM CONTROL
OSD-CLOCK OSD-CLOCK BLOCK DIAGRAM
M26
N23-N25,P25,P26 OSD-R DATA (0-4)
P24,R24-R26,T25,T26 OSD-G DATA (0-5)
T24,U23-U26 OSD-B DATA (0-4)
IC4263 (64M SDRAM)
<FOR IP COVERTER, MULTI WINDOW,
<CLOCK(129MHz)> 3D Y/C SEPARATION, ETC>
DATA BUS(32BIT)
AB1-AB5,AB8,AB11,AC2-AC4,AC8,AD5-AD8,AD11, 64M
AD12,AE4-AE8,AE11,AE12,AF4-AF8,AF10-AF12
MEMORY
1,3,9,15,29,35,41,
43,49,55,75,81
VCC
66
SUB VIDEO SIGNAL VIDEO SIGNAL(MAIN/SUB) CARD Y/PB/PR SIGNAL
+3.3V
IC5950 (LVDS TRANSMITTER)
R DATA (8BIT)
2-4,6,7,54-56 47 PDG4-14
48 PDG4-15
G DATA (8BIT)
8,10-12,14-16,18 45 PDG4-11
TTL PARALLEL
46 PDG4-12
B DATA (8BIT)
TO LVDS SERIAL
19,20,22-25,27,28 41 PDG4-8
CONVERTER
42 PDG4-9
PDG4-2
H-SYNC 37
52 PDG4-3
38
V-SYNC
39 PDG4-5
51
40 PDG4-6
PLL
31
9,26,34,44
VCC
+3.3V
+3.3V
VIDEO SIGNAL PATH I BLOCK DIAGRAM (2/2)
LVDS DATA A(+)
LVDS DATA A(-)
LVDS DATA B(+)
LVDS DATA B(-)
TO VIDEO II
LVDS DATA C(+)
SIGNAL PATH
LVDS DATA C(-)
BLOCK DIAGRAM
LVDS DATA D(+)
LVDS DATA D(-)
LVDS CLOCK(+)
LVDS CLOCK(-)
PT-56DLX75/PT-61DLX75