Table of Contents
Advertisement
CPU & PCI Bus Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
Phoenix-AwardBIOS CMOS Setup Utility
PCI Master 0 WS Write
PCI Delay Transaction
VLink mode selection
VLink 8X Support
DRDY_Timing
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
F5:Previous Values
PCI Master 0 WS Write (Enabled)
This item determines whether the chipsets inserts a delay before any writes from the PCI
slots. If it is enabled, write requests to the PCI bus are executed immediately (with zero wait
states), if the PCI bus is ready to send data.
PCI Delay Transaction (Enabled)
This item is used to meet the latency of PCI cycles to and from the ISA bus.
VLink mode selection (By Auto)
This item controls the data transfer speed between the north and south bridge.
VLink 8X Support (Enabled)
Use this item to enable
or disable VLink 8X support.
DRDY_Timing (Default)
This item specifies
the
timing of data ready.
Press <Esc> to return to the Advanced Chipset Features page.
System BIOS Cacheable (Enabled)
This feature is only valid when the system BIOS is shadowed. It enables or disables the
caching of the system BIOS ROM at F0000h-FFFFFh via the L2 cache. This greatly
speeds up accesses to the system BIOS.
Video RAM Cacheable (Disabled)
Disable or enable this item to read cache data from RAM.
Press <Esc> to return to the main BIOS setting page.
CPU & PCI Bus Control
[Enabled]
[Enabled]
[By Auto]
[Enabled]
[Default]
F6:Fail-Safe Defaults
F7:Optimized Defaults
Using BIOS
Item Help
Menu Level
33
Advertisement
Table of Contents
