Motorola M68MPB334 User Manual page 35

Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued)
Pin
8
9
10
11
12
13
14
15
M68MPB334UM/D
Mnemonic
LAT-DSI / LATCHED INSTRUCTION FETCH (INVERTED) –
(Latched Latched output signal of the inverted state of IFETCH
IFETCH) for CPU32-based MCUs; indicates instruction pipeline
activity.
DSO DEVELOPMENT SERIAL OUT – Serial data output
signal for background debug mode.
INSTRUCTION PIPE for CPU32-based MCUs.
DSI DEVELOPMENT SERIAL IN – Serial data input signal
for background debug mode.
INSTRUCTION FETCH for CPU32-based MCUs.
DSACK1 DATA AND SIZE ACKNOWLEDGE 1 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and external
devices.
DSACK0 DATA AND SIZE ACKNOWLEDGE 0 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and external
devices.
FC2 / FUNCTION CODE 2 – Output signal that identifies the
processor state and address space of the current bus
cycle.
CS5 CHIP SELECT 5 – Output signal that selects peripheral
or memory devices at programmed addresses.
FC1 / FUNCTION CODE 1 – Output signal that identifies the
processor state and address space of the current bus
cycle.
CS4 CHIP SELECT 4 – Output signal that selects peripheral
or memory devices at programmed addresses.
FC0 / FUNCTION CODE 0 – Output signal that identifies the
processor state and address space of the current bus
cycle.
CS3 CHIP SELECT 3 – Output signal that selects peripheral
or memory devices at programmed addresses.
MEVB SUPPORT INFORMATION
Signal
4-5