Fig 28 Block Schematic - Nokia RH-9 Series Ccs Technical Documentation

RH-9
System Module & UI
the range of 3420 to 3840 MHz, and the use of a VCO module enables the possibility of
different vendors for the same component.
PLL Synthesizer, Functional Description
The frequency synthesis PLL in conjunction with the VCO and 2/4 dividers generates the
LO signal for both RX and TX paths, locked to the VCXO which again is locked to the base
station through the AFC.
Input to the PLL is the differential VCO and the 26 MHz reference oscillator signals. The
VCO signal is divided by a swallow counter consisting of a 64/65 dual modulus divider
and NDIV/ADIV dividers. The output of the NDIV/ADIV dividers is re-synchronized in the
phase detector with the output of the dual modulus divider to reduce phase noise.
The reference oscillator signal is divided by the RDIV divider to uptain a 400 kHz signal to
be used as reference in the Phase detector. The output of this divider is also re-synchro-
nized in the phase detector with the reference input to reduce phase noise.
The divided signals are compared in a phase detector, which again controls the charge
pump. The output of the charge pump is connected to the external loop filter.
The average output current of the charge pump is a (piecewise) linear function of the
phase difference between the two input signals to the phase detector with a transfer
constant of approx. 1mA/2π. The transfer characteristic depends on which of the two
available phase detectors is selected.
One detector is the linear phase detector where the current in the current sources of the
charge pump is 1mA independently of phase difference and a completely linear transfer
characteristic is achieved.
The other phase detector is the piecewise linear phase detector where the current is
reduced to 500µA when sourcing and sinking current sources are active simultaneously.
This results in a constant slope transfer characteristic with two discontinuities.
The loop filter averages the pulses from the phase detector and generates a DC control
voltage to the VCO. The loop filter defines the step response of the PLL (settling time),
effects the stability of the loop and perform reference sideband rejection.
All control of the PLL and its sub-circuits, such as the VCO, dividers e.g., is controlled via
the SCU bus from the UPP in the BB section. This also includes the AFC which is per-
formed by the serial data from the UPP.
The following figure shows a simplified block diagram of the Synthesizer
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CCS Technical Documentation
Issue 1 11/02