Fig 17 Intel-Amd Signal Deviations Description - Nokia RH-9 Series Ccs Technical Documentation

RH-9
System Module & UI
RDY O Ready/Busy Output: Similar function as WAIT in the Intel device. Indicates the status of
the read. RDY-low indicates that device is busy and the controller should add wait states.
RDY-high indicates the device is ready for a read operation.
PS I/O Power Save Signal: Indicates whether the bus data should be inverted at the receiving
end. When in input mode, if high, bus data should be inverted in the flash. When high in
output mode, the bus output data should be inverted in the UPP registers. This signal has
no equivalent in the Intel device.
RP# I Hardware Reset Input: Same function as the RST# signal in the Intel device.
Power Save Feature
Intel
The Intel device has two power saving features: Automatic Power Savings (APS) and
standby mode. The device automatically enters APS mode following read cycle comple-
tion. Standby mode is initiated when the device is deselected by driving CE# high, sub-
stantially reducing device power consumption. RST# low also resets the device and puts
it in asynchronous read array mode, provides write protection and clears the status reg-
ister. These two features combined, significantly reduce the power consumption.
AMD
This feature is currently not activated in the hardware configuration software, therefore
the AMD PS feature is not used at all. Gemini tests have shown the benefits offered by this
feature to be rather marginal.
The AMD device implements the standby mode similar to Intel, but uses a designated sig-
nal (PS, IN/OUT) to reduce the number of switchings and thus, the power consumption,
on the MEMADDA[23:0] bus.
Since the internal capacitive load of digital circuits is lower than that of the intercon-
nect level at the PWB, the AMD device uses the PS signal to reduce the amount of
switching on the external bus and transfers the responsibility of signal state change to
the registers inside the flash or the UPP. The PS causes a minimum amount of transitions
on the MEMADD[23:0] bus by performing a bit-wise parity check of the data previously
on the bus with the data to be transmitted. If there are more equal bits than unequal
bits, the data is not inverted before being transmitted and PS remains low. If there are
more unequal bits than equal bits, the data is inverted inside the flash or UPP before
being transmitted on the bus and PS is driven high to indicate the inversion. PS-high at
the receiving end flags the inversion and the received data is inverted inside the flash or
the UPP before being stored or processed. The PS signal is a common signal for all the
devices connected to the MEMADDA[23:0] bus. Below is an example of how this signal
operates.
Page 52 ãNokia Corporation
CCS Technical Documentation
Issue 1 11/02