Nokia RH-9 Series Ccs Technical Documentation page 56

RH-9
System Module & UI
Timing
Address access time is equal to delay from stable addresses to valid output data. In
actual operation it is a fixed number of clock cycles programmed by the SW and depen-
dent on the CLK Frequency.
The chip enable access time is the delay from the stable addresses and stable CE# to
valid data at the output pins.
The output enable access time is the delay from the falling edge of the OE# to valid data
at the output.
Both flashes have a 40 MHz clock rate.
Intel
Some of the more important timing Specifications for the Intel flash are:
Asynchronous Read
Intel AMD
Page 56
Figure 20: Intel Asynchronous Read
ãNokia Corporation
CCS Technical Documentation
Issue 1 11/02