Nokia RH-9 Series Ccs Technical Documentation page 51

CCS Technical Documentation
A/DQ0- A/ I/O
DQ15
CE# I
CLK I
ADV# I
RST# I
OE# I
WE# I
WP# I
WAIT O
Vpp Pwr
Vcc Pwr
VCCQ Pwr
VSSQ Pwr
GND Pwr
AMD
The AMD device has similar signals to the Intel device with a few minor differences in
the naming conventions as listed below. Also, the AMD device uses one additional signal,
PS. This pin is not connected on the Intel device.
Symbol Type Description
Issue 1 11/02
Address/Data Input/Outputs: Multiplexed address/data pins are address inputs while
ADV# is low. When ADV# goes high, address is internally latched and these signals
input/output data. Rising edge of WE# latches write data. Data is output when OE# is
low.
Chip Enable: CE#-low activates internal control logic, I/O buffers and decoders. CE#
high deselects the device, places it in stand-by state and places data and WAIT outputs
at high Z.
Clock: Synchronizes the device to the system bus frequency in synchronous-read con-
figuration and increments an internal burst address generator. During synchronous
read, addresses are latched on ADV# rising edge or clock CLK's rising while AVD# is
low, whichever occurs first.
Address Valid: Indicates valid address presence on address input.
Reset: When low, it resets internal automation and provides data protection during
power transitions by inhibiting write operations. Exit from reset places the device in
asynchronous read mode.
Output Enable: When low, Activates the device's outputs through the data buffers dur-
ing a read cycle. When high, device outputs A/DQ15-0 and WAIT are disabled and
placed in high impedance state.
Write Enable: Controls writes to the device's command user interface and array.
Address and data is latched on the WE#'s rising edge.
Write Protect: Disables/Enables the lock down function when low. Locked down blocks
can not be unlocked through software alone.
WAIT: Indicates data valid in synchronous read modes. It is high-Z until configuration
register bit 10 (WT, Wait Pin Polarity) is written to. With CE# low, WAIT's output can be
either high or low, with CE# high, it is high-Z.
Erase and Program Power: A valid voltage on this pin (see above) allows block erase or
data programming. For in-system (user mode) read, program and erase, Vpp=Vcc.
Vpp=12 V for flashing during production. Extended use of 12V on this pin however,
could damage the block cycling capability. Additionally Vpp serves as write protect if
kept low.
Device power supply
Output Power Supply: Enables all outputs to be driven at VCCQ. This input may be tied
directly to Vcc.
I/O Ground: Should be tied to GND
Ground
Figure 17: Intel-AMD signal deviations description
ãNokia Corporation
RH-9
System Module & UI
Page 51