Kenwood NX-220 Service Manual page 21

5-3. PLL IC (IC403)
The PLL IC compares the differences in phases of the
VCO oscillation frequency and the TCXO reference frequen-
cy, returns the difference to the VCO CV terminal and real-
izes the "Phase Locked Loop" for the return control. This
allows the VCO oscillation frequency to accurately match
(lock) the desired frequency.
When the frequency is controlled by the PLL, the fre-
quency convergence time increases as the frequency differ-
ence increases when the set frequency is changed. To sup-
plement this, the ASIC is used before control by the PLL IC
to bring the VCO oscillation frequency close to the desired
frequency. As a result, the VCO CV voltage does not change
and is always stable at approximately 2.5V.
The desired frequency is set for the PLL IC by the ASIC
(IC610) through the 3-line "SDO1", "PCK_RF", "/PCS_RF"
serial bus. Whether the PLL IC is locked or not is monitored
by the ASIC through the "PLD" signal line. If the VCO is not
the desired frequency (unlocked), the "PLD" logic is low.
The modulation signal of the Low-speed data is applied to
pin 23 of the PLL IC (IC403).
The modulation signal is digital data of a sampling fre-
quency of 96kHz set for the PLL IC by the DSP (IC603)
through the "PLLMOD" line.
5-4. Local switch (D412, D413)
The connection destination of the signal output from the
buffer amplifier (Q408) is changed with the diode switch
(D413) that is controlled by the transmission power supply,
50T, and the diode switch (D412) that is controlled by the
receive power supply, 50R. If the 50T logic is high, it is con-
nected to a send-side pre-drive (Q102). If the 50T logic is
low, it is connected to a receive-side mixer (Q201).
X401
IC403
16.8MHz
TCXO
SDO1
PCK_RF
/PCS_RF
PLLMOD
6. Control Circuit
The control circuit consists of the ASIC (IC610) and its pe-
ripheral circuits. IC610 mainly performs the following:
1) Switching between transmission and reception by PTT
signal input.
2) Reading system, zone, frequency, and program data from
the memory circuit.
CIRCUIT DESCRIPTION /
Q401,Q402
D402~D405
D407,D409~D411
Loop
Filter
PLL
IC404 (1/2)
CV
VCO MOD
IC402
ASSIST
100C
Fig. 6 PLL block diagram / 图 6 PLL 结构图
电路说明
5-3. PLL IC(IC403)
P L L I C 对比 V C O 震荡频率和 T C X O 基准频率的相位差，将
相位差返回至 VCO CV 端子， 从而实现反馈控制的 "锁相环路" 。
这样可以使 VCO 震荡频率与所需的频率精确匹配 ( 锁定 )。
频率由 P L L 控制时，频率锁定时间将随着设定频率改变时
频率差的增大而增加。为对此进行补充，在由 PLL IC 控制之
前使用 A S I C 以使 V C O 震荡频率接近所需的频率。因此，V C O
CV 的电压不变，始终稳定在约 2.5V。
PLL IC 的所需频率由 ASIC(IC610) 通过 3 线"SDO1" 、 " PCK_
R F" 、 "/ P C S _ R F"串行总线进行设置。P L L I C 是否锁定由
ASIC 通过"PLD"信号线路进行监测。如果 VCO 不是所需的频
率 ( 失锁 )，则"PLD"逻辑变低。
低速数据调制信号被加载到 PLL IC(IC403) 的第 23 脚。
调制信号是 DSP(IC603) 通过"PLLMOD"线路为 PLL IC 设
置的 96kHz 采样频率的数字数据。
5-4. 本振开关 (D412, D413)
缓冲放大器 ( Q408) 输出信号的连接目标由发射电源 50T 控
制的二极管开关 ( D413) 和接收电源 50R 控制的二极管开关
( D412) 进行切换。如果 50T 逻辑为高，则被连接到发送侧预
驱动 ( Q102)。如果 50T 逻辑为低，则被连接到接收侧混频器
(Q201)。
Q405 Q408
D415
BUFF BUFF
VCO
AMP AMP
50CS
Doubler
BPF
6. 控制电路
控制电路由 A S I C ( I C610) 和外围电路组成。I C610 主要执
行以下功能 ：
1) 由输入的 PTT 信号切换发射和接收。
2) 从存储电路读取系统、区域、频率和编程数据。
NX-220
D412,D413
T/R
to TX stage
SW
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