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P5HX-A
Peer Concurrency - Determines the CPU allowed to run DRAM/L2 cycles or not
when non-PHLD PCI master devices are targeting peer device . The available
options are:
•
Enabled (default)
Chipset Special Features - Enable/Disable chipset special features . The
available options are:
•
Enabled (default)
DRAM ECC/PARITY Select - Allows users to configure the DRAM error check
method. The available options are:
•
Parity (default)
Memory Parity/ECC Check - Determines the memory check function
nabled" or
isabled" and the function can enable only under the DRAM with
parity bit support . Otherwise , please select
whether DRAM support DRAM ECC/Parity function . The available options are:
•
Disabled (default)
•
Auto
L2 Cache Cacheable Size - Determines the L2 cache cacheable size 64MB or
512MB . The available options are:
•
64MB (default)
Chipset NA# Asserted - Determines to enable the Next Address (NA#) cycle or
not . The available options are:
•
Enabled (default)
User's Manual 1-28
•
Disabled
•
Disabled
•
ECC
uto" . BIOS can auto-detect
•
Enabled
•
512MB
•
Disabled
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