Table of Contents
Advertisement
Chapter 6: Solving Problems
If you see unexplained states in the trace list
If you see unexplained states in the trace list
Check to see that the sequence, storage and trigger specifications are set up to
exclude the states that you don't need.
If you are using the built-in terminal interface, try using the tl <instruction_state>
<operand_state> command to inform the dequeuer which operand state belongs
with the named instruction state.
If you are using the built-in terminal interface, try using the -ol option to the tl
command to begin disassembly from the low word of the starting state, instead of
the high word.
Check to see if instruction or operand accesses in the range covered by the trace
could be filled from cache memory. If so, these cycles won't appear in the trace
list, which will confuse the disassembler. Either disable the cache memory entirely
or disable caching for those address ranges by adding the ci (cache inhibit) attribute
to those ranges in the memory map.
If the analyzer won't trigger
Instruction fetches from internal 68360 resources normally aren't visible to the
analyzer. You can force them to be visible by enabling show cycles. The SIM
register MCR allows you to set show cycles.
When the MC68360 fetches instructions from program memory, it can addresse
32-bit longwords. These addresses are multiples of 4 (ending in 0h, 4h, 8h, and
Ch). The instruction you are trying to trigger on may be in the high word or the
low word of the long word. If you specify trigger on a symbolic address without
knowing whether that symbol is in the high word or low word, the address may not
appear on the address bus. If you think this may be the problem, try specifying
your trigger symbol as long-aligned. This long-word correction is not necessary
when you are trying to trigger on data fetches; data is always fetched from the
absolute address of the data location.
119
Advertisement
Table of Contents
