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Chapter 4:Connecting the Emulator to a Target System
Selecting a clock module
At this point, the problem is to find the faulty bus cycle that eventually caused a
recognizable problem. The same situation exists if the processor stops execution at
an address that should not have been executed, or if a program is simply running
code incorrectly.
There are really only two ways to go about determining what is wrong. One is to
try to trace back the terminal error condition to a faulty bus cycle. The other is to
start at the beginning of the trace, or at some other known point, and work forward,
comparing the trace to the execution that was expected while looking for the point
where execution first becomes unexpected. A listing of the program or a tracelist
captured by a preprocessor could be used for this comparison.
When you find a suspected bus cycle, set up a trigger on it so that you can make a
timing measurement on the cycle. When looking for clues or shortcuts to the
problem, keep in mind that a system is usually made up of many different types of
memory devices: ROM, EEPROM, SRAM, DRAM, and peripheral ports. Each of
these devices may have different timing characteristics. Also, keep in mind that
unique characteristics of a bus cycle, such as size, and number of wait states, may
result in unique timing requirements.
Fixing timing problems
When a timing problem is identified, you must decide how to fix it. First, examine
the signal to make sure that signal quality is not affecting the timing. Look for AC
or DC drive problems or reflections caused by transmission line problems. If you
can find no other solution to the problem, you may have to lower the clock speed.
Buffering the AS, DS, and RW signals by configuring "cf asdsrw=buf" may
improve signal quality and even timing on these signals. If there are problems
associated with these signals this should be tried. The same goes for problems
related to the clock. Try configuring "cf clko1=buf" if there are timing problems
associated with the clock.
If the timing problem only occurs during data accesses, another possible solution is
to add wait states to the memory access. This assumes that the problem is with the
amount of time it takes to access the memories in the system and is not a problem
with a setup time to a synchronous circuit. A good indicator of this type of
problem is when the data setup time to the emulator is being missed.
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