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2 REGISTERS
The V flag is set under the following conditions:
(1) When negative integers are added together, the operation produced a 0 (positive) in the sign bit (most
significant bit of the result)
(2) When positive integers are added together, the operation resulted in a 1 (negative) in the sign bit (most
significant bit of the result)
(3) When a negative integer is subtracted from a positive integer, the operation resulted in producing a 1
(negative) in the sign bit (most significant bit of the result)
(4) When a positive integer is subtracted from a negative integer, the operation resulted in producing a 0 (positive)
in the sign bit (most significant bit of the result)
Z (bit 1): Zero
This bit indicates that an operation resulted in 0. More specifically, this bit is set to 1 when the execution of a
logical operation, arithmetic operation, or shift instruction resulted in 0, or is otherwise reset to 0.
N (bit 0): Negative
This bit indicates a sign. More specifically, the most significant bit (bit 31) of the result of a logical operation,
arithmetic operation, or shift instruction is copied to this N flag. If the operation being executed is step division,
the sign bit of the division is set in the N flag, which affects the execution of the division.
6
EPSON
S1C33 FAMILY C33 PE CORE MANUAL
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