Yamaha RX-V381 Service Manual page 91

A B C
1
DIGITAL 3/5
A U P _ B C K
2
A U P _ W C K
A U P _ S D 0
to DIGITAL 1/5
H D M I _ W C K / D L 2
H D M I _ S D 1 / D R 1
H D M I _ S D 2 / D L 1
H D M I _ S D 3 / D R 0 / S P F
H D M I _ S D 3 / D R 0 / S P F
H D M I _ D R 2
D I R _ M C K 1
D I R _ B C K
to DIGITAL 4/5
3 D I R _ W C K
D I R _ S D O
A/D IN
D S P _ N _ R D Y
D S P _ N _ R D Y
D S P _ M I S O
D S P _ M I S O
D S P _ M O S I
D S P _ M O S I
D S P _ S C K
D S P _ S C K
to DIGITAL 2/5
D S P _ N _ I N T
D S P _ N _ I N T
D S P _ N _ C S
D S P _ N _ C S
4
D S P _ N _ R S T
D S P _ N _ R S T
D S P _ F M T
D S P _ F M T
5
6
7
I C / C B / X L : 2 4 1 -
O H T E R : 2 4 0 1 -
D I G I T A L 3 : D S P
8
9
N O T I C E
( m o d e l ) R E S I S T O R
J J A P A N
R E M A R K S P A R T S N A M E
U U . S . A
N O M A R K C A R B O N F I L M R E S I S T O R ( P = 5 )
C C A N A D A
C A R B O N F I L M R E S I S T O R ( P = 1 0 )
R G E N E R A L
M E T A L O X I D E F I L M R E S I S T O R
T C H I N A
M E T A L F I L M R E S I S T O R
K K O R E A
M E T A L P L A T E R E S I S T O R
A A U S T R A L I A
F I R E P R O O F C A R B O N F I L M R E S I S T O R
B B R I T I S H
C E M E N T M O L D E D R E S I S T O R
G S T A N D A R D
S E M I V A R I A B L E R E S I S T O R
L S I N G A P O R E
C H I P R E S I S T O R
E S O U T H E U R O P E
★ All voltages are measured with a 10M Ω /V DC electronic voltmeter.
V T A I W A N
F R U S S I A N C A P A C I T O R ★ Components having special characteristics are marked ⚠ and must be replaced
P L A T I N A M E R I C A R E M A R K S P A R T S N A M E
with parts having specifications equal to those originally installed.
10 S B R A Z I L N O M A R K E L E C T R O L Y T I C C A P A C I T O R
H T H A I T A N T A L U M C A P A C I T O R
★ Schematic diagram is subject to change without notice.
N O M A R K C E R A M I C C A P A C I T O R
C E R A M I C T U B U L A R C A P A C I T O R
P O L Y E S T E R F I L M C A P A C I T O R
● 電圧は、内部抵抗 10M Ωの電圧計で測定したものです。
P O L Y S T Y R E N E F I L M C A P A C I T O R
M I C A C A P A C I T O R
● ⚠印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
P P O L Y P R O P Y L E N E F I L M C A P A C I T O R
パーツリストに記載されている部品を使用してください。
S E M I C O N D U C T I V E C E R A M I C C A P A C I T O R
P O L Y P H E N Y L E N E S U L F I D E F I L M
S ● 本回路図は標準回路図です。改良のため予告なく変更することがあります。
C A P A C I T O R
D E F
A U P _ B C K
A U P _ W C K
A U P _ S D 0
H D M I _ S D 1 / D R 1
H D M I _ S D 2 / D L 1
H D M I _ D R 2
D I R _ M C K 1
D I R _ B C K
D I R _ W C K
D I R _ S D O
+ 1 . 2 D S P
R S V 2
1 3 3
U S B 0 _ V D D A 1 2
1 3 4
FL/FR
C/SW
U S B 0 _ V D D A 1 8
1 3 5
L 2 4 0 1
N C
1 3 6
C 2 4 0 2 B K P 1 0 0 5 H S 6 8 0 - T C 2 4 0 6 C 2 4 0 7
U S B 0 _ D P
1 0 0 0 P ( B )
0 . 1 / 1 0 ( B J ) 0 . 0 1 / 1 6 ( B ) 1 3 7
U S B 0 _ D M
1 3 8
L 2 4 0 2
N C
B K P 1 0 0 5 H S 6 8 0 - T 1 3 9
U S B 0 _ V D D A 3 3
C 2 4 0 4 X L 2 4 1
1 8 P ( C H ) 2 0 M H Z 1 4 0
P L L 0 _ V D D A
1 4 1
D G N D
P L L 0 _ V S S A
1 4 2
O S C I N
1 4 3
C 2 4 0 5 O S C V S S
1 4 4
1 8 P ( C H )
J 2 4 0 2 O S C O U T
1 4 5
0
D S P _ N _ R S T R 2 4 0 1 R E S E T
1 4 6
1 0 0 C 2 4 0 8
C V D D
1 4 7
R 2 4 0 2 0 . 1 / 1 0 ( B J ) R T C _ X I
1 4 8
C 2 4 0 9
1 0 0 K R T C _ C V D D
1 4 9
N _ T R S T 0 . 1 / 1 0 ( B J ) T R S T
1 5 0
C 2 4 1 0
D V D D
1 5 1
T M S 0 . 1 / 1 0 ( B J ) T M S
1 5 2
T D I T D I
1 5 3
C 2 4 1 1
C V D D
1 5 4
T C K 0 . 1 / 1 0 ( B J ) T C K
1 5 5
T D O T D O
1 5 6
G P 7 [ 1 4 ]
1 5 7
0 . 1 / 1 0 ( B J ) C 2 4 1 2 D V D D
1 5 8
C V D D
1 5 9
0 . 1 / 1 0 ( B J ) C 2 4 1 3
A H C L K X 1
1 6 0
C 2 4 1 4
C V D D
1 6 1
0 . 1 / 1 0 ( B J ) A C L K X 1
1 6 2
A F S X 1
1 6 3
C 2 4 1 5
D V D D
1 6 4
D I R _ B C K 0 . 1 / 1 0 ( B J ) A C L K R 1
1 6 5
D I R _ W C K A F S R 1
1 6 6
C 2 4 1 6
C V D D
1 6 7
0 . 1 / 1 0 ( B J ) A X R 1 [ 8 ]
1 6 8
A X R 1 [ 7 ]
1 6 9
A X R 1 [ 6 ]
1 7 0
H D M I _ W C K / D L 2 A X R 1 [ 5 ]
1 7 1
C 2 4 1 7
D V D D
1 7 2
H D M I _ S D 3 / D R 0 / S P F 0 . 1 / 1 0 ( B J ) A X R 1 [ 4 ]
1 7 3
H D M I _ S D 2 / D L 1 A X R 1 [ 3 ]
1 7 4
H D M I _ S D 1 / D R 1 A X R 1 [ 2 ]
1 7 5
D I R _ S D O A X R 1 [ 1 ]
1 7 6
H D M I _ D R 2
C 2 4 2 1
n o _ u s e
R 2 4 0 9
n o _ u s e
R 2 4 1 3
C B 2 4 1
9 1 0 K
T M S T M S
1
N _ T R S T N _ T R S T
2
T D I T D I S e r i a l F l a s h M e m o r y
3 8 7 6 5
P D ( + 3 . 3 V ) ( 8 M b i t s ) Y H 6 7 0 A 0
+ 3 . 3 D S P 1 4
1 2 3 4
T D O T D O
5 W r i t t e n b y Y A M A H A : Y H 6 7 0 A 0
D G N D
D G N D 6
T C K T C K
7
8
D G N D
n o _ u s e
B l a n k p r o d u c t o f I C 2 4 2 i s a a l t e r n a t e
o f t w o p r o d u c t s b e l o w .
P a r t N o . V e n d e r P a r t T y p e
Y D 7 6 2 B 0 W I N B O N D W 2 5 Q 8 0 D V S S I G
Y E 0 0 5 B 0 E O N E N 2 5 Q 8 0 B - 1 0 4 H I P
Details of colored lines
Red / full line: Power supply (+)
Red /dashed line: Power supply (-)
Orange: Signal detect
Yellow: Clock
Green: Protection detect
Brown: Reset signal
Blue: Panel key input
G H
C 2 4 3 0 C 2 4 4 3
n o _ u s e
n o _ u s e
R 2 4 1 2
3 3 X 4
E M B _ S D C K E E M C K E
8 8
D V D D C 2 4 4 6
SL/SR 8 7
E M B _ C L K
0 . 1 / 1 0 ( B J ) E M C L K
8 6
E M B _ W E _ D Q M [ 1 ] E M D Q M 1
8 5
E M B _ D [ 8 ]
E M D 8
8 4
E M B _ D [ 9 ] /
E M D 9
8 3
E M B _ D [ 1 0 ] E M D 1 0
8 2
D V D D C 2 4 4 7
8 1
E M B _ D [ 1 1 ]
0 . 1 / 1 0 ( B J ) E M D 1 1
8 0
E M B _ D [ 1 2 ] E M D 1 2
7 9
E M B _ D [ 1 3 ]
E M D 1 3
7 8
C V D D C 2 4 4 8
AUDIO DSP
7 7
E M B _ D [ 1 4 ] 0 . 1 / 1 0 ( B J ) E M D 1 4
7 6
C 2 4 4 9
D V D D
7 5
E M B _ D [ 1 5 ] 0 . 1 / 1 0 ( B J ) E M D 1 5
7 4
E M B _ D [ 0 ] E M D 0
7 3
E M B _ D [ 1 ] E M D 1
7 2
C 2 4 5 0
D V D D
7 1
E M B _ D [ 2 ] 0 . 1 / 1 0 ( B J ) E M D 2
7 0
C 2 4 5 1
C V D D
6 9
E M B _ D [ 3 ] 0 . 1 / 1 0 ( B J ) E M D 3
I C 2 4 1 6 8
C 2 4 5 2
C V D D
D 8 0 Y K 1 1 3 D P T P 4 0 0 6 7
E M B _ D [ 4 ] 0 . 1 / 1 0 ( B J ) E M D 4
Y D 9 9 8 D 0 6 6
C 2 4 5 3
D V D D
6 5
E M B _ D [ 5 ] 0 . 1 / 1 0 ( B J ) E M D 5
6 4
E M B _ D [ 6 ] E M D 6
6 3
E M B _ D [ 7 ] E M D 7
6 2
C 2 4 5 4
C V D D R 2 4 4 1
6 1
4 7 X 4
E M B _ W E _ D Q M [ 0 ] 0 . 1 / 1 0 ( B J ) E M D Q M 0
6 0
E M B _ W E / E M W E
D G N D 5 9 C 2 4 5 5
D V D D / E M C A S
5 8
E M B _ C A S 0 . 1 / 1 0 ( B J )
5 7
C 2 4 5 6
C V D D
5 6
E M A _ W E 0 . 1 / 1 0 ( B J )
5 5
E M A _ D [ 7 ]
No replacement part available. 5 4
C 2 4 5 7
D V D D
サービス部品供給なし
5 3
0 . 1 / 1 0 ( B J )
E M A _ D [ 6 ]
5 2
E M A _ D [ 5 ]
5 1
C 2 4 5 8
C V D D
5 0
E M A _ D [ 4 ] 0 . 1 / 1 0 ( B J )
4 9
E M A _ D [ 3 ]
4 8
C 2 4 5 9
D V D D
4 7
E M A _ D [ 2 ] 0 . 1 / 1 0 ( B J )
4 6
E M A _ D [ 1 ]
4 5
C 2 4 3 7 C 2 4 3 9
n o _ u s e n o _ u s e + 1 . 2 D S P + 3 . 3 D
+ 3 . 3 D S P 1
R 2 4 2 7
n o _ u s e
R 2 4 2 8
4 . 7 K
D G N D
4 . 7 K X 4
R 2 4 2 9
+ 3 . 3 D S P 1
R 2 4 2 1
S E R I A L F L A S H B O O T
1 0 K
IC242 : W25Q80DVSSIG
8 M-bit flash memory with dual and quad SPI
Security Register 3 - 0
0 0 3 0 0 0 h
R 2 4 2 2
0 0 2 0 0 0 h
1 0 K 0 0 1 0 0 0 h
0 0 0 0 0 0 h
Block Segmentation
0FFF00h
xxFF00h xxFFFFh
Block 15 (64KB)
Sector 15 (4KB)
0F0000h
xxF000h xxF0FFh
xxEF00h xxEFFFh
Sector 14 (4KB)
xxE000h xxE0FFh
xxDF00h xxDFFFh
Sector 13 (4KB)
xxD000h xxD0FFh
xx2F00h xx2FFFh
Sector 2 (4KB)
xx2000h xx20FFh
08FF00h
xx1F00h xx1FFFh
Block 8 (64KB)
Sector 1 (4KB)
080000h
xx1000h xx10FFh
xx0F00h xx0FFFh 07FF00h
Sector 0 (4KB)
Block 7 (64KB)
xx0000h xx00FFh
070000h
Write Control
/WP(IO 2 ) 3
Logic
Status
Register
High Voltage
Generators
00FF00h
Block 0 (64KB)
/HOLD(IO ) 7
3 000000h
Page Address
CLK 6
Latch / Counter Beginning
SPI Page Address
/CS 1 Command
and
Column Decode
Control Logic
And 256-Byte page Buffer
Data
DI(IO 0 ) 5
DO(IO 1 ) 2
Byte Address
Latch / Counter
I J K
S B L / S B R T I _ S D S B
T I _ S D S B
S R L / S R R T I _ S D S
T I _ S D S
C / S W T I _ S D C
T I _ S D C
to DIGITAL 4/5
F L / F R T I _ S D F
T I _ S D F
T I _ W C K
T I _ W C K
T I _ B C K
T I _ B C K
IC243: A3V64S40GTP
1M x 16-bit x 4 banks synchronous DRAM
CLK
Clock
+ 3 . 3 D S P 1
SDRAM 64 Mbit
Generator
CKE
C 2 4 6 9
1 0 / 1 0 Address
C 2 4 7 3
n o _ u s e
C 2 4 6 7
0 . 1 / 1 0 ( B J )
V D D V S S
D Q 0 D Q 1 5
R 2 4 4 2 R 2 4 4 4
4 7 X 4 4 7 X 4
E M D 0 V D D Q V S S Q E M D 1 5
CS
E M D 1 D Q 1 D Q 1 4 E M D 1 4
E M D 2 D Q 2 D Q 1 3 E M D 1 3
RAS
E M D 3 V S S Q V D D Q E M D 1 2
D Q 3 D Q 1 2
CAS
D Q 4 D Q 1 1
R 2 4 4 3 R 2 4 4 5
4 7 X 4 4 7 X 4
E M D 4 V D D Q V S S Q E M D 1 1
WE
E M D 5 D Q 5 D Q 1 0 E M D 1 0
E M D 6 D Q 6 D Q 9 E M D 9
E M D 7 V S S Q V D D Q E M D 8
D Q 7 D Q 8
C 2 4 6 4 V D D V S S
E M D Q M 0 D Q M L N C
0 . 1 / 1 0 ( B J )
/ E M W E W E D Q M U E M D Q M 1
C 2 4 1 8
/ E M C A S n o _ u s e C A S C K E M C L K
/ E M R A S R A S C K E E M C K E
/ E M C S C S N C
E M B A 0 B A 0 A 1 1 E M A 1 1
E M B A 1 B A 1 A 9 E M A 9
E M A 1 0 A 1 0 A 8 E M A 8
E M A 0 A 0 A 7 E M A 7
E M A 1 A 1 A 6 E M A 6
E M A 2 A 2 A 5 E M A 5
E M A 3 A 3 A 4 E M A 4
V D D V S S
C 2 4 6 8
0 . 1 / 1 0 ( B J )
C 2 4 7 4
D G N D
n o _ u s e
S D R A M 6 4 M b i t
I C 2 4 3 a l t e r n a t e t h r e e p r o d u c t s b e l o w .
P a r t N o . V e n d e r P a r t T y p e
Y D 4 8 7 C 0 Z E N T E L A 3 V 6 4 S 4 0 G T P - 6 0
X 9 6 2 5 C 0 E S M T M 1 2 L 6 4 1 6 4 A - 5 T G 2 Y
Y F 5 8 7 A 0 E T R O N E M 6 3 8 1 6 5 T S D - 6 G
0 0 3 0 F F h
0 0 2 0 F F h
0 0 1 0 F F h
0 0 0 0 F F h
0FFFFFh
0F00FFh
08FFFFh
0800FFh
07FFFFh
0700FFh
00FFFFh
0000FFh
Ending
Page Address
L M N
RX-V381/HTR-3069
Bank D
Bank C
Bank B
Row
Address
Buffer
Mode Bank A
and
Register
Refresh
Counter
Sense Amplifier
L(U)DQM
Column
Column Decoder
Address
Buffer
and
Refresh
Counter
DQ
Data Control Circuit
1 54
VDD VSS
2 53
DQ0 DQ15
3 52
VDDQ VSSQ
DQ1 4 51 DQ14
5 50
DQ2 DQ13
6 49
VSSQ VDDQ
7 48
DQ3 DQ12
8 47
DQ4 DQ11
VDDQ 9 46 VSSQ
45
DQ5 10 DQ10
11 44
DQ6 DQ9
12 43
VSSQ VDDQ
DQ7 13 42 DQ8
VDD 14 41 VSS
40
LDQM 15 NC
16 39
WE UDQM
17 38
CAS CLK
RAS 18 37 CKE
CS 19 36 NC
35
A13 20 A11
21 34
A12 A9
22 33
A10/AP A8
A0 23 32 A7
A1 24 31 A6
30
A2 25 A5
26 29
A3 A4
VDD 27 28 VSS
91