Yamaha RX-V381 Service Manual page 65

Function Name
No.
(P.C.B.)
128 DVDD
129 AHCLKR0/GP2[14]/BOOT[11]
130 ACLKR0/ECAP1/APWM1/GP2[15]
131 AFSR0/GP3[12]
132 AMUTE1/EPWMTZ/GP4[14]
133 RSV2
134 USB0_VDDA12
135 USB0_VDDA18
136 NC
137 USB0_DP
138 USB0_DM
139 NC
140 USB0_VDDA33
141 PLL0_VDDA
142 PLL0_VSSA
143 OSCIN
144 OSCVSS
145 OSCOUT
146 RESET
147 CVDD
148 RTC_XI
149 RTC_CVDD
150 TRST
151 DVDD
152 TMS
153 TDI
154 CVDD
155 TCK
156 TDO
157 GP7[14]
158 DVDD
159 CVDD
160 AHCLKX1/EPWM0B/GP3[14]
161 CVDD
162 ACLKX1/EPWM0A/GP3[15]
163 AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
164 DVDD
165 ACLKR1/ECAP2/APWM2/GP4[12]
166 AFSR1/GP4[13]
167 CVDD
168 AXR1[8]/EPWM1A/GP4[8]
169 AXR1[7]/EPWM1B/GP4[7]
170 AXR1[6]/EPWM2A/GP4[6]
171 AXR1[5]/EPWM2B/GP4[5]
172 DVDD
173 AXR1[4]/EQEP1B/GP4[4]
174 AXR1[3]/EQEP1A/GP4[3]
175 AXR1[2]/GP4[2]
176 AXR1[1]/GP4[1]
I/O
I/O McASP0 receive master clock
I BOOT[11]
I/O McASP0 receive bit clock
I/O Enhanced capture 1 input or auxiliary PWM 1 output
I/O McASP0 receive frame sync
I/O McASP1 mute output
I/O eHRPWM0 trip zone input
I/O eHRPWM1 trip zone input
I/O eHRPWM2 trip zone input
Reserved. For proper device operation, this pin must be tied directly to
PWR
CVDD or left unconnected [do not connect to ground (VSS)].
PWR USB0 PHY 1.2-V LDO output for bypass cap
PWR USB0 PHY 1.8-V supply input
- -
A USB0 PHY data plus
A USB0 PHY data minus
- -
PWR USB0 PHY 3.3-V supply
PWR PLL analog VDD (1.2-V filtered supply)
GND PLL analog VSS (for filter)
I Oscillator input
GND Oscillator ground (for filter only)
O Oscillator output
I Device reset input
I Low-frequency (32-kHz) oscillator receiver for real-time clock
PWR RTC module core power ( isolated from rest of chip CVDD)
I JTAG test reset
I JTAG test mode select
I JTAG test data input
I JTAG test clock
O JTAG test data output
I/O General-Purpose IO signal
I/O McASP1transmit master clock
I/O eHRPWM0 B output
I/O McASP1transmit bit clock
I/O eHRPWM0 A output
I/O McASP1transmit frame sync
I/O Sync input to eHRPWM0 module or sync output to external PWM
I/O McASP1receive bit clock
I/O Enhanced capture 2 input or auxiliary PWM 2 output
I/O McASP1receive frame sync
I/O McASP1 serial data
I/O eHRPWM1 A output (with high-resolution)
I/O McASP1 serial data
I/O eHRPWM1 B output
I/O McASP1 serial data
I/O eHRPWM2 A output (with high-resolution)
I/O McASP1 serial data
I/O eHRPWM2 B output
I/O McASP1 serial data
I eQEP1B quadrature input
I/O McASP1 serial data
I eQEP1A quadrature input
I/O McASP1 serial data
I/O McASP1 serial data
RX-V381/HTR-3069
Detail of Function
65