Tlcs-870 Family - Toshiba TLCS-900 Family Product Manual

TLCS-870
One instruction cycle operated in a single clock cycle
The core architecture is configured to reduce the number of clock cycles
required to complete one machine cycle to a single clock cycle. This achieves
processing performance four times that of TLCS-870/C Series at the same
internal clock frequency.
Internal clock
TLCS-870/C
Series
TLCS-870/C1
Series
TLCS-870/C1 Series: Minimum instruction execution time of 125 ns
TLCS-870/C Series: Minimum instruction execution time of 250 ns
*The minimum instruction execution time is reduced by half compared to TLCS-870/C.
Noise reduction measures
The TLCS-870 Family implements various measures for improving noise immunity.
Separate power supplies
Internal VDD
Internal
logic
Internal VSS
I/O VDD
I/O
buffer
I/O VSS
Separate power supplies are used for internal
logic and I/O.
Internal EMI noise can be prevented from
propagating to I/O pins.
Oscillator protection
Oscillator pins
OSC
Xin Xout
High-frequency noise can be eliminated by
placing a noise filter.
48
Family
NEW
1 2 3 4
One machine cycle
1
One machine cycle
Decoupling capacitor
Prevents internal
noise from
propagating
to I/O pins.
A decoupling capacitor is attached to the noise source.
High-frequency currents directly flowing to
power supply lines can be reduced.
Spurious noise can be suppressed by minimizing
current loops created by circuit operations.
Pin
Filter
External pin noise
Spike noise can be eliminated.
870/C1 Series road map
[TLCS-870/C1 Series]
ROM
96KB
60KB
32KB
16KB
Packages:
UG: 64-pin LQFP (10 mm x 10 mm/0.50-mm pitch)
FG: 64-pin QFP (14 mm x 14 mm/0.80-mm pitch)
Part Number
TMP89CM60UG/FG
TMP89CS60UG/FG
TMP89FS60UG/FG
Enables power supply
Circuit
decoupling and current
block
loop minimization.
Noise filter
Filter
Prevents noise
propagation.
Noise-free internal signal
(planned)
Standard product LCD driver built-in
42-pin 44-pin 48-pin 64-pin 80-pin 100-pin
Flash version or mask version can be selected.
ROM RAM
++
3.0 KB
32 KB
++
3.0 KB
60 KB
3.0 KB
60 KB
++
: Under development : Under planning
Optimized pin layout
(VSS)
VSS XIN XOUT TEST
C1 C2
X'TAL
Oscillator pins are guarded by GND pins.
Spurious noise from oscillator pins can be
suppressed.
NEW
VDD