32-Bit Tx System Risc - Toshiba TLCS-900 Family Product Manual

32 TX System RISC
-bit
TX19
Quick interrupt response
Conventional RISC processor
Software processing
Decide interrupt level
Set CPU registers
Jump to vector address
Save general-purpose registers on stack
Save SFRs on stack
Read entry address
Jump to entry address
Enable interrupts
Use of hardware for
part of interrupt processing
Excellent code efficiency
The TX19A core features the MIPS16e-TX architecture that realizes enhanced code efficiency and performance.
TX19
MIPS16
Displays outstanding efficiency in control programs heavy with bit operations.
42
Family
Hardware processing
Save general-purpose registers on stack
TM
MIPS16e
16-/32-bit
10 20 %
(compared to conventional
Toshiba RISC CPU core)
Code efficiency of the
highest level in RISC
TX19A
MIPS16e-TX
TX19
Decide interrupt level
Set CPU registers
Jump to vector address
Software processing
Save SFRs on stack
Read entry address
Jump to entry address
Enable interrupts
Automated interrupt processing
reduces burden on software.
MIPS16e-TX
Toshiba-defined
extended instructions
16-/32-bit
Architecture
New instructions are added to enable bit manipulation,
format conversion, and saving/restoring multiple registers.
Addition of CP0 instructions allows all processing to be
performed with only MIPS16e-TX.
Shadow registers
Compiler
The compiler tailored to TX19A is provided.
TX19A
Hardware processing
Decide interrupt level
Set CPU registers
Jump to vector address
Save general-purpose registers on stack
Software processing
Save SFRs on stack
Read entry address
Jump to entry address
Enable interrupts