Mep (Media Embedded Processor) - Toshiba TLCS-900 Family Product Manual

Media embedded Processor
MeP
Media embedded Processor (MeP) is a processor for media processing based on Toshiba's original architecture.
Given its flexible configuration and extensibility, MeP can be customized for targeted applications.
Overview of the MeP Core
MeP core is a configurable and extensibile processor core.
32-bit RISC architecture
High code efficiency due to 32-bit/16-bit variable length
instructions
Supports optional instructions and other configuration
items
Supports interface for hardware extensions
Fully-synthesizable design not dependent on process
technology
High performance and low power consumption
Configuration Items
It is possible to set up the optimum configuration by
selecting the optional instructions or cache memory size
required for media processing.
Optional instructions
32-bit multiplication/division, bit manipulation, zero
detection, differential absolute value, and others
Memory configuration
Instruction cache: 0 to 16 Kbytes (Direct-mapped or 2-way)
Data cache: 0 to 16 Kbytes (Direct-mapped or 2-way)
Instruction RAM: 0 to 32 Kbytes
Data RAM: 0 to 128 Kbytes
Interrupt controller: 1 to 32 interrupt sources and
1, 3, 7, or 15 priority levels
Timer/counter: 0 to 4 channels
Debug support function
Bus width: 32 or 64 bits
MeP Module
MeP Core
Interrupt
Timer/Counter
Controller
Debug
Optional
Support Instructions
32-bit Base Processor
Instruction
Bus I/F Data RAM/
RAM/
Unit Cache
Cache
Global Bus I/F
40
MeP Module
Extensions
UCI Unit
Hardware
DSP Unit
Engine
VLIW
Coprocessor
Local Bus
DMAC
* For more information, please visit http://www.MePcore.com/.
Hardware Extensions
Application-specific extensions can be connected to the
MeP core for high-performance processing.
User-customized instruction (UCI) unit
Customized instructions for single-cycle arithmetic
operations.
DSP unit
Customized instructions for multi-cycle arithmetic
operations.
Can access Internal data RAM of MeP core.
Simultaneous two-bank access to data RAM of MeP core.
VLIW coprocessor
Works as a 2-way or 3-way VLIW processor with the MeP
core.
Hardware engines
Extensible control registers (up to 4K words for each)
Development Environment
Third-party vendors provide the software development
environments that support the configuration items and
hardware extensions described here.
MeP integrator
Language tools (C/C++ compiler, assembler, and linker)
Simulator
Debugger
Evaluation board
The MeP module is a processor module customized for
specific applications.
MeP core
Configurable processor core
Extensions
Four kinds of hardware extensions
Multiple extensions
Local bus
Internal data bus in MeP module
Hierarchical bus structure for higher transfer efficiency
DMAC
Transfers data between the global bus and MeP core or
extensions.
Global bus I/F
Provides a bus bridge for connection to on-chip bus.