64-Bit Tx System Risc; Tx49 Family - Toshiba TLCS-900 Family Product Manual

64-Bit TX System RISC

TX49
Family
The TX49 Family of RISC microprocessors for embedded use is an original Toshiba 64-bit processor family and is
based on the RISC architecture designed by MIPS Technologies, Inc. The customer can implement a custom SoC us-
ing the TX49 Family cores in conjunction with general-purpose ASSP products.
64-bit RISC architecture
R4000A architecture
Upward-compatible instruction set including MIPS I,
MIPS II and MIPS III instruction set architectures (ISAs)
TX49/H2: Internal operating frequency: 200 MHz
TX49/H3: Internal operating frequency: 300 MHz/333 MHz
TX49/H4: Internal operating frequency: 400 MHz
TX49/L3: Internal operating frequency: 200 MHz
TX49/L4: Internal operating frequency: 333 MHz
(Under development)
TX49/W4: Internal operating frequency: 400 MHz
(Under development)
Level 2 cache of up to 256 Kbytes can be installed (optional)
Non-blocking load function
The instructions which follow the instruction currently
being executed are executed while the cache is being refilled.
DSP function
Thirty-two 64-bit general-purpose registers
Optimized 5-stage pipelining
Single- or double-precision floating-point unit (FPU)
(TX49/H2, TX49/H3, TX49/H4 and TX49/W4 core)
Debug support unit (DSU)
Supports EJTAG.
First product incorporating the TX49/L3 core
TMPR4951BFG-200
64-bit RISC microprocessor offering excellent cost performance
The TMPR4951BFG incorporates a 0.13- m process TX49/L3 core,
and by minimizing the built-in functions and external interfaces, it of-
fers the industry's highest cost-performance ratio in the 200 MHz
class and low-power consumption, all encapsulated in a compact pack-
age. Moreover, the SysAD bus interface adopted for this microprocessor
enables diverted use of existing resources and facilitates system devel-
opment. These and other features make it an ideal controller for low-
end LBPs, networks, and settop boxes.
Integer Arithmetic
Clock
Generator
Unit
64-Bit
General-
Purpose
Registers
Sync Circuit
Integer
Arithmetic
Data Path
Debug
Multiplier/
Support Unit
Accumulator
(EJTAG)
Unit
16-KB 4-Way
Set-Associative
SysAD Bus
Interface Instruction Cache
TX49/L3 Core
System Control
Coprocessor
Coprocessor
Registers
Memory Management
Pipeline
Unit
Control
48 Double-Entry TLBs
Exception
Handling Unit
8-KB 4-Way
Cache
Set-Associative
Controller
Data Cache
Low-power consumption design
Low-power consumption modes (Doze/Halt)
Built-in high-capacity primary cache
Instruction cache: 32 Kbytes
4-way set-associative
Lock function supported
Data cache: 32 Kbytes
4-way set-associative
Lock function supported
Write-back/write-through (every page)
Can be used as a CPU core for custom SoC
TX49/H2: 0.18-µm process technology
TX49/H3, TX49/L3: 0.13-µm process technology
TX49/H4, TX49/L4, TX49/W4: 90-nm process technology
Complete development environment
TX49/L3 64-bit RISC core
Five-stage pipeline
On-chip caching
4-way set-associative caches
Instruction cache: 16 Kbytes built in
Data cache: 8 Kbytes built in
Cache lock function
48 double-entry
External bus (32-bit SysAD bus)
Low-power consumption mode
Debug support unit (DSU) built in
(execution control only)
Maximum operating frequency:
Core: 200 MHz
External bus: 100 MHz
I/O supply voltage: 2.5 V or 3.3 V
Internal supply voltage: 1.5 V
Package: 100-pin LQFP
(14 mm x 14 mm, 0.5-mm pitch)
Write
Buffer
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