Figure 3-5. Dio Channel Configured For High Dio Power-Up State With External Load - National Instruments PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections
PC-DIO-96/PnP User Manual
PC-DIO-96/PnP
82C55

Figure 3-5. DIO Channel Configured for High DIO Power-up State with External Load

Example:
At power up, the board is configured for input and, by default, all DIO
lines are high. To pull one channel low, follow these steps:
1. Install a load (R
L
greater the current consumption and the lower the voltage (V).
2. Using the following formula, calculate the largest possible load to
maintain a logic low level of 0.4 V and supply the maximum
driving current (I).
⇒ R
V = I * R
L
V= 0.4 V
I = 46 µA + 10 µA
Therefore:
R = 7.1 kΩ
L
This resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO
line at power up. You can substitute smaller resistor values, but they
will draw more current, leaving less drive current for other circuitry
connected to this line. The 7.1 kΩ resistor reduces the amount of a logic
high source current by 0.4 mA with a 2.8 V output.
+5 V
100 kΩ
GND
). Remember that the smaller the resistance, the
= V / I, where:
L
; Voltage across R
; 4.6 V across the 100 kΩ pull-up
resistor and 10 µA from 82C55
leakage current
; 0.4 V / 56 µA
3-10
Digital I/O Line
R
L
L
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