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THEORY OF OPERATION
4.3
POWER MONITOR AND RESET
The board reset strobe is provided by a Texas Instruments* TL7705A power supply monitor. The
TL7705A senses board voltage and ensures that the board RESET and RESET signals remain asserted
for several milliseconds after board power is stable (above 4.6 V). The TL7705A also asserts RESET
and RESET when the board voltage drops below 4.6 V.
A reset push-button manually triggers the TL7705A to reset the board.
The Cyclone EP requires only the +5V power supply. +12V is only necessary when programming the
Flash ROM. The PCI-SDK Platform receives power from the edge connector; no external power
supplies are required.
The +5V power LED (D2) indicates that the board power is stable. This LED is OFF when the board
voltage drops below 4.6 V.
4.4
I/O INTERFACE
I/O design features include:
•
Shares control logic between all devices
•
Low cost, low complexity control logic
•
Uses standard PLDs
•
Isolates I/O subsystem from other board functions
The I/O and peripheral subsystems provide the interface and timing control for all peripherals and
registered I/O devices on the Cyclone EP. The design is simplified considerably by combining the
control for all peripheral and registered I/O devices.
The I/O section includes the following features:
•
Flash ROMs (28F020)
•
Serial Port (16C550 UART)
•
Counter/Timers (Z8536 CIO)
•
Parallel Port (74ABT logic and a 22V10 PAL)
The control logic for the I/O devices is located in the iFX780 Flex Logic device. This logic generates
chip select, read and write strobes, and ready back to the processor. The data signals and A3:2 address
signals have been buffered to avoid excessive loading of the processor's signals.
4-2
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