Yamaha CL3 Service Manual page 90

CL3/CL1
KSZ8051RNL (YD367B00) PHY
PIN
NAME I/O
NO.
1 -
GND
2 -
VDD_1.2
3 VDDA_3.3 -
4 RXM I/O
5 I/O
RXP
6 I/O
TXM
7 I/O
TXP
8 XO O
9 XI I
10 REXT I
11 I/O
MDIO
12 I
MDC
13 I/O
RXD3/
PHYAD0
14 I/O
RXD2/
PHYAD1
15 I/O
RXD1/
PHYAD2
16 I/O
RXD0/
DUPLEX
17 VDDIO -
18 RXDV/ I/O
CONFIG2
SN75LVDS84ADGGR
PIN
NAME I/O
NO.
90
FUNCTION
Ground
1.2V core V
DD
3.3V analog V
DD
Physical receive or transmit signal (- differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (- differential)
Physical transmit or receive signal (+ differential)
Crystal feedback – for 25 MHz crystal
Crystal / Oscillator / External Clock Input
Set physical transmit output current
Management Interface (MII) Data I/O
Management Interface (MII) Clock Input
MII Mode: MII Receive Data Output[3]/
Config Mode: The pull-up/pull-down value is latched
as PHYADDR[0] at the de-assertion of reset
MII Mode: MII Receive Data Output[2]/
Config Mode: The pull-up/pull-down value is latched
as PHYADDR[1] at the de-assertion of reset
MII Mode: MII Receive Data Output[1]/
Config Mode: The pull-up/pull-down value is latched
as PHYADDR[2] at the de-assertion of reset
MII Mode: MII Receive Data Output[0]/
Config Mode: The pull-up/pull-down value is latched
as DUPLEX at the de-assertion of reset
3.3V, 2.5V or 1.8V digital V
DD
MII Mode: MII Receive Data Valid Output/
Config Mode: The pull-up/pull-down value is latched
as CONFIG2 at the de-assertion of reset
LVDS TRANSMITTER
FUNCTION
PIN
NAME I/O
NO.
19 RXC/ I/O MII Mode: MII Receive Clock Output/
B-CAST_OFF Config Mode: The pull-up/pull-down value is latched
as B-CAST_OFF at the de-assertion of reset
20 RXER/ I/O MII Mode: MII Receive Error Output/
ISO Config Mode: The pull-up/pull-down value is latched
as ISOLATE at the de-assertion of reset
21 INTRP/ I/O Interrupt Output: Programmable Interrupt Output
NAND_Tree# Config Mode: The pull-up/pull-down value is latched
as NAND Tree# at the de-assertion of reset.
MII Mode: MII Transmit Clock Output
22 TXC I/O
MII Back-to-Back Mode: MII Transmit Clock Input
23 TXEN I MII Mode: MII Transmit Enable Input
24 TXD0 I MII Mode: MII Transmit Data Input[0]
25 TXD1 I MII Mode: MII Transmit Data Input[1]
MII Mode: MII Transmit Data Input[2]
26 TXD2 I
27 TXD3 I MII Mode: MII Transmit Data Input[3]
28 COL/ I/O MII Mode: MII Collision Detect Output /
CONFIG0 Config Mode: The pull-up/pull-down value is latched
as CONFIG0 at the de-assertion of reset
29 CRS/ I/O MII Mode: MII Carrier Sense Output /
Config Mode: The pull-up/pull-down value is latched
CONFIG1
as CONFIG1 at the de-assertion of reset
30 LED0/ I/O LED Output: Programmable LED0 Output /
NWAYEN Config Mode: Latched as Auto-Negotiation Enable
(register 0h, bit 12) at the de-assertion of reset
LED Output: Programmable LED1 Output /
31 LED1/ I/O
SPEED Config Mode: Latched as SPEED (register 0h, bit
13) at the de-assertion of reset
32 RST# I/O Chip Reset (active low)
PADDLE GND - Ground
PIN
NAME I/O
NO.
CPU: IC402
FUNCTION
FUNCTION