Data Frame Of Firmware Commands - Texas Instruments MSP430 User Manual

Data Frame
Received
MSP-
GANG430 HDR
Firmware
Command
Load
80
Parameters
Start 80
Transmit
80
Diagnostic
GANG430
responds on
80
Transmit
Diagnostic
Erase Image 80
Load Image
80
Block
Load Image
80
Checksum
Execute Self
80
Test
Set Signals 80
Erase
80
Firmware
Load
Firmware 80
Block
Finalize
80
Firmware
Select Baud
80
Rate
Write Target
80
Selective
Read Target
80
Selective
(1)
All numbers are bytes in hexadecimal notation. ACK is sent by the MSP-GANG430. The synchronization sequence (TX = 0x80,
RX = 0x90) is not part of the data frame. It must precede every frame.
(2)
HDR: DATA_FRAME = 0x80 means data frame expected in accordance with TI MSP430
serial standard protocol (SSP).
CMD: Command identification
L1, L2: Number of bytes consisting of AL through Dn. The valid values of these bytes are
restricted as follows: L1 = L2, L1 < 255, L1 even.
A1, A2, Block start address or erase (check) address or jump address LO/HI byte. The bytes
A3: are combined to generate a 24-bit word as follows: Address = A3 × 0x10000 + A2 ×
0x100 + A1
LL, LH: Number of pure data bytes (maximum 250) or erase information LO/HI byte or block
length of erase check (maximum is 0xFFFF)
D1...Dn: Data bytes
CLK, 16-bit checksum LO/HI byte
CKH:
xx: Can be any data
–: No character (data byte) received/transmitted
ACK: The acknowledge character returned by the MSP-GANG430 can be either
DATA_ACK = 0x90 (frame was received correctly, command was executed
successfully) or DATA_NAK = 0xA0 (frame not valid (e.g., wrong checksum, L1 ≠ L2),
command is not defined, is not allowed, or was executed unsuccessfully).
n: Number of bytes
26
Firmware
Table 3-1. Data Frame of Firmware Commands
CMD L1 L2 A1
36 08 08 D1
31 06 06 00
32 04 04 00
00 1E 1E D1
33 06 06 00
34 n n A1
37 n n D1
35 06 06 00
30 04 04 D1
39 04 04 D1
3A n n AL
3B 04 04 00
38 06 06 D1
3C n n A1
3D 08 08 A1
Copyright © 2003–2010, Texas Instruments Incorporated
A2 A3 A4 LL LH
D2 D3 D4 D5 D6
00 – – 00 00
00 – – 00 00
D2 – – D3 D4
00 – – 00 00
A2 A3 00 n–6 00
D2 – – D3 D4
00 – – 00 00
D2 – – D3 D4
D2 – – D3 D4
AH – – n–4 00
00 – – 00 00
00 – – 00 00
A2 A3 00 n–6 00
A2 A3 00 n 00
SLAU101O – March 2003 – Revised May 2010
www.ti.com
(1) (2)
D1 D2...Dn CKL CKH
00 00 CKL CKH
00 00 CKL CKH
– – CKL CKH
D5 D06...D1E CKL CKH
00 00 CKL CKH
D1 D2...Dn–6 CKL CKH
D5 D6...Dn CKL CKH
00 00 CKL CKH
– – CKL CKH
– – CKL CKH
D1 D2...Dn–4 CKL CKH
– – CKL CKH
00 00 CKL CKH
D1 D2...Dn–6 CKL CKH
D1 D2 CKL CKH
ACK
ACK
ACK
–
–
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
–