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RM46L852
SPNS185 – SEPTEMBER 2012
5.3
Enhanced Quadrature Encoder (eQEP)
Figure 5-4
shows the eQEP module interconnections on the device.
EPWM1/../7
Connection
Selection
Mux
5.3.1 Clock Enable Control for eQEPx Modules
Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST
is active low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper
state. When SYS_nRST goes in-active high, the state of clock enable is respected.
ePWM Module Instance
eQEP1
eQEP2
The default value of the control registers to enable the clocks to the eQEPx modules is 1. This means that
the VCLK4 clock connections to the eQEPx modules are enabled by default. The application can choose
to gate off the VCLK4 clock to any eQEPx module individually by clearing the respective control register
bit.
5.3.2 Using eQEPx Phase Error to Trip ePWMx Outputs
The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs
EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection
multiplexor. This multiplexor is defined in
multiplexor is inverted and connected to the TZ4n trip-zone input of all EPWMx modules. This connection
allows the application to define the response of each ePWMx module on a phase error indicated by the
eQEP modules.
124
Peripheral Information and Electrical Specifications
VBus32
EQEP1ENCLK
VCLK4
SYS_nRST
EQEP1INTn
VIM
EQEP1ERR
VBus32
EQEP2ENCLK
VCLK4
SYS_nRST
EQEP2INTn
VIM
Figure 5-4. eQEP Module Interconnections
Table 5-11. eQEPx Clock Enable Control
Control Register to Enable Clock
PINMMR40[16]
PINMMR40[24]
Table
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EQEP1
Module
EQEP1SOE
EQEP2
Module
EQEP2SOE
5-3. As shown in
Figure
5-1, the output of this selection
Copyright © 2012, Texas Instruments Incorporated
www.ti.com
EQEP1A
EQEP1B
EQEP1I
EQEP1IO
EQEP1IOE
EQEP1S
EQEP1SO
Mux
EQEP2A
EQEP2B
EQEP2I
EQEP2IO
EQEP2IOE
EQEP2S
EQEP2SO
Default Value
1
1
IO
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