Enhanced Quadrature Encoder (Eqep) - Texas Instruments TMS570LS0 32 Series Manual

TMS570LS0432, TMS570LS0332
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
7.8

Enhanced Quadrature Encoder (eQEP)

Figure 7-14 shows the eQEP module interconnections on the device.
CDDISx.9
VCLK
ACK
CLKSTOP_REQ
SYS_nRST
nEQEPERR
_SYNC
NHET
nDIS
GIOA[5]
7.8.1 Clock Enable Control for eQEPx Modules
The device level control of the eQEP clock is accomplished through the enable/disable of the VCLK clock
domain for eQEP only. This is realized using bit 9 of the CLKDDIS register. The eQEP clock source is
enabled by default.
7.8.2 Using eQEPx Phase Error
The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs
EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection
multiplexor. As shown in
the N2HET module. This connection allows the application to define the response to a phase error
indicated by the eQEP modules.
7.8.3 Input Connections to eQEPx Modules
The input connections to each of the eQEP modules can be selected between a double-VCLK-
synchronized input or a double-VCLK-synchronized and filtered input, as shown in
INPUT SIGNAL
eQEPA
eQEPB
eQEPI
eQEPS
94 Peripheral Information and Electrical Specifications
VBUSP Interface
EQEPENCLK
EQEP
VCLK
CLK
GATE
EQEPINTn
VIM
EQEPERR
VCLK2
Figure 7-14. eQEP Module Interconnections
Figure 7-14, the output of this selection multiplexor is inverted and connected to
Table 7-17. Device-Level Input Synchronization
CONTROL FOR DOUBLE-SYNCHRONIZED
CONNECTION TO eQEPx
PINMMR8[0] = 1
PINMMR8[8] = 1
PINMMR8[16] = 1
PINMMR8[24] = 1
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Product Folder Links: TMS570LS0432 TMS570LS0332
EQEP
Module
NHETnDIS_SEL
CONTROL FOR DOUBLE-SYNCHRONIZED
AND FILTERED CONNECTION TO eQEPx
PINMMR8[0] = 0 and PINMMR8[1] = 1
PINMMR8[8] = 0 and PINMMR8[9] = 1
PINMMR8[16] = 0 and PINMMR8[17] = 1
PINMMR8[24] = 0 and PINMMR8[25] = 1
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EQEPA
EQEPB
EQEPI
EQEPIO
EQEPIOE
EQEPS
MUX
EQEPSO
CTRL
EQEPSOE
Table 7-17.
I/O