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PhA
PhB
clk
clkdiv
dir
pos
-1 -1 -1 -1 -1 -1 -1 -1 -1
rel
+1
Figure 24-3. Quadrature Encoder and Velocity Predivider Operation
The period of the timer is configurable by specifying the load value for the timer in the QEI Timer Load
(QEILOAD) register. When the timer reaches zero, an interrupt can be triggered, and the hardware
reloads the timer with the QEILOAD value and continues to count down. Lower encoder speeds require a
longer timer period to capture enough edges to have a meaningful result. At higher encoder speeds, both
a shorter timer period and/or the velocity predivider can be used.
Equation 66
converts the velocity counter value into an rpm value:
VELDIV
rpm = (clock × (2
where
•
clock is the controller clock rate
•
ppr is the number of pulses per revolution of the physical encoder
•
edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CAPMODE clear and 4 for
CAPMODE set)
For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder is
attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of ÷1
(VELDIV is clear) and clocking on both PhA and PhB edges, this results in 81920 pulses per second (the
motor turns 10 times per second). If the timer were clocked at 10000 Hz, and the load value was 2500
(1/4 of a second), it would count 20480 pulses per update. Using the above equation:
rpm = (10000 × 1 × 20480 × 60) ÷ (2500 × 2048 × 4) = 600 rpm
Now, consider that the motor is sped up to 3000 rpm. This results in 409600 pulses per second, or
102400 every 1/4 of a second. Again, the above equation gives:
rpm = (10000 × 1 × 102400 × 60) ÷ (2500 × 2048 × 4) = 3000 rpm
Care must be taken when evaluating this equation because intermediate values may exceed the capacity
of a 32-bit integer. In the above examples, the clock is 10000 and the divider is 2500; both could be
predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if they were
compile-time constants, they could also be reduced to a simple multiply by 4, cancelled by the ÷4 for the
edge-count factor.
NOTE: Reducing constant factors at compile time is the best way to control the intermediate values
of this equation and reduce the processing requirement of computing this equation.
The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a simple
shift can therefore be done in place of the division. For encoders with a power of 2 pulses per revolution,
the load value can be a power of 2. For other encoders, a load value must be selected such that the
product is very close to a power of 2. For example, a 100 pulse-per-revolution encoder could use a load
value of 82, resulting in 32800 as the divisor, which is 0.09% above 2
an adequate approximation of the divide in most cases. If absolute accuracy were required, the
microcontroller's divide instruction could be used.
The QEI module can produce a controller interrupt on several events: phase error, direction change,
reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt status,
interrupt status, and interrupt clear capabilities are provided.
SLAU723A – October 2017 – Revised October 2018
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+1 +1 +1 +1 +1 +1 +1 +1
+1
+1
+1
) × SPEED × 60) / (LOAD × ppr × edges)
Copyright © 2017–2018, Texas Instruments Incorporated
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+1
+1
+1
14
. In this case a shift by 15 would be
Quadrature Encoder Interface (QEI)
Functional Description
+1
(66)
(67)
(68)
1571
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