Enhanced Quadrature Encoder (Eqep) - Texas Instruments TMS570LS0714 Manual

www.ti.com
7.4

Enhanced Quadrature Encoder (eQEP)

Figure 7-8 shows the eQEP module interconnections on the device.
EPWM1/../7
Connection
Selection
Mux
A. For more detail on the eQEP input synchronization selection of the EQEPxA/B pins to each eQEPx module, see
Figure 7-9.
Figure 7-9 shows the detailed input synchronization selection (asynchronous, double-synchronous, or
double-synchronous + filter width) for eQEPx.
eQEPx
(x = 1 or 2)
7.4.1 Clock Enable Control for eQEPx Modules
Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST
is active-low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper
state. When SYS_nRST goes in-active high, the state of clock enable is respected.
The default value of the control registers to enable the clocks to the eQEPx modules is 1 (see
This means that the VCLK4 clock connections to the eQEPx modules are enabled by default. The
application can choose to gate off the VCLK4 clock to any eQEPx module individually by clearing the
respective control register bit.
Copyright © 2013–2016, Texas Instruments Incorporated
VBus32
EQEP1ENCLK
VCLK4
SYS_nRST
EQEP1INTn
VIM
EQEP1ERR
VBus32
EQEP2ENCLK
VCLK4
SYS_nRST
EQEP2INTn
VIM
Figure 7-8. eQEP Module Interconnections
Figure 7-9. eQEPx Input Synchronization Selection Detail
Submit Documentation Feedback
Product Folder Links:
SPNS226E – JUNE 2013 – REVISED NOVEMBER 2016
EQEP1
Module
EQEP1SOE
EQEP2
Module
EQEP2SOE
double
sync
6 VCLK4
Cycles Filter
Peripheral Information and Electrical Specifications
TMS570LS0714
TMS570LS0714
EQEP1A
EQEP1B
EQEP1I
EQEP1IO
EQEP1IOE
EQEP1S
EQEP1SO
Mux
EQEP2A
EQEP2B
EQEP2I
EQEP2IO
EQEP2IOE
EQEP2S
EQEP2SO
EQEPxA or EQEPxB
(x = 1 or 2)
Table
IO
7-15).
105