Texas Instruments TMS320 User Manual page 99

3.6.4 Interrupt Latency
4) Run your program. Any change to the value at the top of the stack is seen
as a non-zero total (or maximum) in the corresponding STS object.
Interrupt latency is the maximum time between the triggering of an interrupt
and when the first instruction of the HWI executes. You can measure interrupt
latency for the timer interrupt by following the appropriate steps for your
platform:
Note:
It is currently not possible to calculate interrupt latency on the C5500 using
DSP/BIOS because the C55x timer access is outside data space.
1) Configure the HWI object specified by the CPU Interrupt property of the
CLK Manager to monitor a Data Value.
2) Set the addr parameter to the address of the timer counter register for the
on-device timer used by the CLK Manager.
3) Set the type to unsigned.
4) Set the operation parameter to STS_add(*addr).
5) Set the Host Operation parameter of the corresponding STS object,
HWI_INT14_STS, to A * X + B. Set A to 4 and B to 0.
1) Configure the HWI_TINT object to monitor the tim register.
2) Set the operation parameter to STS_add(*addr).
3) Set the host operation parameter of the HWI_TINT_STS object to A*x +
B. Set A to -1 and B to the value of the PRD register.
The STS objects HWI_TINT_STS (C5000) or HWI_INT14_STS (C6000) then
display the maximum time (in instruction cycles) between when the timer
interrupt was triggered and when the Timer Counter Register was able to be
read. This is the interrupt latency experienced by the timer interrupt. The
interrupt latency in the system is at least as large as this value.
Implicit DSP/BIOS Instrumentation
Instrumentation 3-37