Texas Instruments TMS320 User Manual page 117

Hardware Interrupts
❏ Single Instruction state
❏ Run state
Debug Halt State: This state is entered through a break event, such as the
decoding of a software breakpoint instruction or the occurrence of an analysis
breakpoint/watchpoint or a request from the host processor.
When halted, time-critical interrupts can still be serviced. An interrupt is
defined as time critical interrupt/real-time interrupt if the interrupt has been
enabled in the IER and DBGIER register. Note that the INTM bit is ignored in
this case.
However, the DBGM bit can be used to prevent the CPU from entering the
halt state (or perform debug access) in undesirable regions of code. If INTM
and DBGM are used together, then it is possible to protect regions of code
from being interrupted by any type of interrupt. It also ensures that debugger
updates of registers/memory cannot occur in that region of code.
SETC INTM, DEGM
/ Uninterruptable, unhaltable region of code
CLRC INTM, DBGM
If the breakpoint is present in real-time, it halts the CPU and causes it to enter
into DEBUG HALT mode. This is identical to the behavior of breakpoints
when in stopmode. Note that software breakpoints replace the original
instruction -- so it is not possible to safely ignore or delay the software
breakpoint's execution; otherwise, you will not be executing the intended set
of instructions. However, other forms of causes of halting the CPU can be
delayed. It's important to note that placing software breakpoints is a
"deliberate act" -- you know exactly where you are going to halt, whereas with
other forms of halting (such as via the CCS Halt command or a watchpoint or
other triggering event), the user will often not know where in the program
execution the halt will occur.
The user should never place breakpoints in locations where interrupts or halts
are forbidden. However, it is possible that a halt from CCS could be initiated
when the CPU is in the uninterruptible, unhaltable region of code, in which
case the halt will be delayed until DBGM is no longer set. This is just like an
interrupt, which will be delayed until INTM is no longer set.
As an example, assume there is a variable called Semaphore, which is
incremented in an ISR, and decremented in the main loop. Because of the
way interrupts and debug accesses are handled, neither can occur in the
italicized regions below:
Thread Scheduling 4-13