JBL ES250PW Service Manual page 33

ES250PW
Philips Semiconductors
8-bit parallel-in/serial-out shift register
FEATURES
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Output capability: standard
• I
category: MSI
CC
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q
Q ) available from the last stage. When the parallel load
7
(PL) input is LOW, parallel data from the D
D inputs are loaded into the register asynchronously.
7
QUICK REFERENCE DATA
GND = 0 V; T
amb
SYMBOL
t / t
PHL PLH
f
max
C
I
C
PD
Notes
1. C is used to determine the dynamic power dissipation (P
PD
P = C
D PD
f = input frequency in MHz
i
f = output frequency in MHz
o
∑ (C × V
L CC
C = output load capacitance in pF
L
V = supply voltage in V
CC
2. For HC the condition is V
For HCT the condition is V
ORDERING INFORMATION
See "74HC/HCT/HCU/HCMOS Logic Package Information"
Downloaded from www.Manualslib.com
0
= 25 °C; t
= t = 6 ns
r f
PARAMETER
propagation delay
CP to Q Q
7, 7
PL to Q Q
7, 7
D to Q Q
7 7, 7
maximum clock frequency
input capacitance
power dissipation capacitance per
package
× V × f + ∑ (C × V
2 2
CC i L CC
× f
2
) = sum of outputs
o
= GND to V
I CC
= GND to V
I CC
manuals search engine
When PL is HIGH, data enters the register serially at the
D input and shifts one place to the right
s
→ Q → Q
(Q
0 1
transition. This feature allows parallel-to-serial converter
expansion by tying the Q
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
and
7
to
APPLICATIONS
• Parallel-to-serial data conversion
CONDITIONS
C = 15 pF; V = 5 V
L CC
notes 1 and 2
in µW):
D
× f
) where:
o
− 1.5 V
.
32
Product specification
74HC/HCT165
, etc.) with each positive-going clock
2
output to the D
7 S
TYPICAL
HC HCT
16 14
15 17
11 11
56 48
3.5 3.5
35 35
input of the
UNIT
ns
ns
ns
MHz
pF
pF