Toshiba GRL100-701B Instruction Manual page 261

• Press 5 (=Logic circuit) on the Test screen to display the Logic circuit screen.
• Enter 59 as a signal number to be observed at monitoring jack A and press the ENTER key.
Residual current level detection is verified as follows:
• Apply three-phase rated voltage and single-phase test current IT (= 3 Io ).
Set IT to lag V a by DEFF characteristic angle DEF θ . (The default setting of DEF θ is 85°.)
•
Lower V a to 10 V to generate a residual voltage. Changing the magnitude of IT while
retaining the phase angle with the voltages, and measure the current at which the element
operates. Check that the measured current magnitude is within ± 5% of the current setting.
V c
Residual voltage level detection is verified as follows:
•
Set IT to rated current and the three-phase voltage to rated voltage. Lower the magnitude of
V a while retaining the phase angle with the current and measure the voltage V a at which the
element operates. Operating residual voltage is expressed by (VR-V a ), where VR is the rated
voltage. Check that the (VR-V a ) is within 5% of the residual voltage setting.
6.5.1.6 Inverse Definite Minimum Time Overcurrent Element (IDMT) OCI, EFI
The testing circuit is shown in Figure 6.5.1.8.
Single-phase
current
source
+
DC
power
supply −
Start
Time
counter
Stop
OV
One of the four inverse time characteristics can be set, and the output signal numbers of the
IDMT are as follows:
V a
V a
IT
θ
V b
3V o
A
Figure 6.5.1.8 Testing IDMT
 260 
6 F 2 S 0 8 5 0
GRL100
TB1
-1
I a
-2
-7
3I o
-8
A
Monitoring
jack
TB4 -A16
0V
-A17
E