Input And Output Status When Failure Occurs; Output Status For Cpu Stop - Mitsubishi Electric CC-Link IE Basic Reference Manual

Input and output status when failure occurs

This section describes the status of input from a data link faulty station and output status of cyclic data if a stop error occurs in
the CPU module.
Status
Input status from data link faulty station
Cyclic data output when a stop error occurs in the CPU module
Master station
RX
Slave station 1
Slave station 2
Slave station 3
RY
Slave station 1
Slave station 2
Slave station 3
RWw
Slave station 1
Slave station 2
Slave station 3
RWr
Slave station 1
Slave station 2
Slave station 3
: Area where the input from a faulty station is cleared
: Area where the operation (clear/hold) differs depending on the CPU module
: Area where data is held
: Area where the operation depends on the settings on the slave station side

Output status for CPU STOP

The following are cyclic data outputs when the CPU module is in the STOP state.
• MELSEC iQ-R, MELSEC-Q/L: Data is held. However, when the device set to perform link refresh is Y device, the data is
cleared.
• MELSEC iQ-F: Data is cleared.
7 FUNCTIONS
32
7.1 Cyclic Transmission
Operation
RX is cleared. Regarding RWr, the data before an error occurs is held.
• MELSEC iQ-R, MELSEC-Q/L: Data is held.
• MELSEC iQ-F: Data is cleared.
Slave station 1 Slave station 2
RX RX
RY RY
RWw RWw
RWr RWr
Slave station 3
RX
RY
RWw
RWr