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Texas Instruments TMS320F2837 D Series Errata Sheet

Texas Instruments TMS320F2837 D Series Errata Sheet

Dual-core mcus silicon revisions c, b, a, 0
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1
Introduction
This document describes the silicon updates to the functional specifications for the TMS320F2837xD
microcontrollers (MCUs).
The updates are applicable to the following:
337-ball New Fine Pitch Ball Grid Array, ZWT Suffix
176-pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack, PTP Suffix
2
Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
[TMS320] DSP devices and support tools. Each TMS320™ DSP commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F28379D). Texas Instruments recommends two
of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX
for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PTP) and temperature range (for example, T).
SPRZ412K – December 2013 – Revised February 2020
Submit Documentation Feedback
TMS320F2837xD Dual-Core MCUs
Silicon Revisions C, B, A, 0
TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0
Copyright © 2013–2020, Texas Instruments Incorporated
SPRZ412K – December 2013 – Revised February 2020
Silicon Errata
1

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Summary of Contents for Texas Instruments TMS320F2837 D Series

  • Page 1 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
  • Page 2: Device Markings

    F = Flash DEVICE 28379D 28378D 28377D 28376D 28375D 28374D Figure 2. Example of Device Nomenclature TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 3 ISR. Failing to do so may cause undefined behavior of CPU execution. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 4 Mode 2: This option is unavailable when using GPIO qualification. This mode is not recommended for either GPIO ASYNC or GPIO qualification. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 5 Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity I2C: SDA and SCL Open-Drain Output Buffer Issue SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 6 Advisory — ePIE: Spurious VCU Interrupt (ePIE 12.6) Can Occur When First Enabled ........Advisory — eQEP: Position Counter Incorrectly Reset on Direction Change During Index TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 7 Advisory — McBSP: McBSP Transmit in SPI Slave Mode ........Advisory — Crystal: Maximum Equivalent Series Resistance (ESR) Values are Reduced SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 8 For simplicity, it is recommended that 500 µs be used as the power-up time for both CMPSS and GPDAC. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 9 1 (minimum) and 1023 (maximum) while observing the system clock on the XCLOCKOUT pin. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 10 // the ADCINTOVF here so the external routine will detect the // condition. AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; // clear OVF TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 11 This will result in enough delay that the second channel will always read the fresh ADC result. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 12 For the revisions affected, the S+H duration should be chosen to account for the Workaround(s) additional switch resistance. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 13 (that is, use ESD mats, wrist-straps, ionizers, and so forth). If ADC performance becomes degraded, replace the device. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 14 ADC input model. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 15 128 codes, in sets of up to 4 missing codes in a row. None Workaround(s) SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 16 VREG. This will not impact device operation. DDIO None Workaround(s) TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 17 All applications should follow the restrictions outlined in this advisory. Contact TI for Workaround(s) devices already in production which violate this advisory. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 18 5. CPU1 will refrain from accessing the flash until CPU2 releases ownership of the flash pump semaphore. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 19 Beginning with revision C silicon, the Boot ROM will perform the above workaround before branching to the application. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 20 Configure GPIO inputs configured as eQEP pins for non-asynchronous mode (any Workaround(s) GPxQSELn register option except “11b = Asynchronous”). TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 21 The workaround can also be applied at the System level by a supervisor resetting the device if it is not responding. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 22 The latest released C2000Ware, which has this workaround implemented, can be used as reference. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 23 If the number of samples is less than or equal to N, clear the SDIFLG register; otherwise, do not clear the SDIFLG register to prevent further SDFM interrupts. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 24 5. Enable the SDFM X-BAR trip events in the corresponding X-BAR registers (ePWM X- BAR or GPIO X-BAR event). TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 25 3. Delay for at least a latency of data filter + 5 SD-Cx clock cycles. 4. Enable the SDFM data filter. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 26 Figure 4. Pipeline Diagram of the Issue When There are no Stalls in the Pipeline TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 27 ; FPU register read of R6H Figure 6 shows the pipeline diagram with the workaround in place. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 28 Figure 6. Pipeline Diagram With Workaround in Place TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 29 PIE group (PIE group 12) may inadvertently be missed. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 30 // from an FPU operation (not EISQRTF32/EINVF32) // Handle Overflow/Underflow condition // Ack the interrupt and exit TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 31 C code, the user must consider these flags to be unreliable, and therefore, neither poll these flags in code nor trigger interrupts off of them. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 32 V and V supply sequencing. DDOSC TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 33 Workaround 3: An external 82-Ω resistor can be added to the board between V SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 34 SCL and SDA terminals. The placement of the series termination resistor and pullup resistor should be connected as shown in Figure TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 35 200 µA Maximum high-level input 6600 current up to 100 µA SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 36 2. Do not use DBRED/DBFED = 0 if in Shadow Load Mode. This is for both RED and FED. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 37 // Delay of 50 SYSCLK Cycles C2000Ware_3_00_00_00 and later revisions will have this workaround implemented. SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 38 The CMPIN4N, CMPIN4P, CMPIN5N, and CMPIN5P functions are not available on the Details silicon revisions affected. None Workaround(s) TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 39 GpioCtrlRegs.GPxDIR.bit.GPIOx = 1; // To tri-state the GPIO(logic 1),set GPIO as input GpioCtrlRegs.GPxDIR.bit.GPIOx = 0; SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 40 PCB level timing requirements of these pins. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 41 DCAN FIFO mode. None Workaround(s) SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 42 Apply external clock source to X1 on silicon revision B devices, even if using INTOSC as Workaround(s) the application clock source. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 43 McBSP in SPI Slave mode receives data properly from the master. Do not transmit data using SPI Slave mode of the McBSP. Workaround(s) SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 44 Crystal shunt capacitance (C0) should be less than or equal to 7 pF. None Workaround(s) TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 45: Documentation Support

    For more information regarding the TMS320F2837xD devices, see the following documents: • TMS320F2837xD Dual-Core Microcontrollers Data Manual • TMS320F2837xD Dual-Core Microcontrollers Technical Reference Manual SPRZ412K – December 2013 – Revised February 2020 TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 46 Documentation Support www.ti.com Trademarks PowerPAD, TMS320 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. TMS320F2837xD Dual-Core MCUs Silicon Revisions C, B, A, 0 SPRZ412K – December 2013 – Revised February 2020 Submit Documentation Feedback...
  • Page 47: Revision History

    Boot ROM: Calling SCI Bootloader from Application advisory......... • Section 4.2: Added Boot ROM: Using CPU1 Wait Boot or CPU2 Idle Mode advisory. SPRZ412K – December 2013 – Revised February 2020 Revision History Submit Documentation Feedback Copyright © 2013–2020, Texas Instruments Incorporated...
  • Page 48 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated...

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