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Setting
The CPU cycle is only deferred after being held in Snoop Stall for 31 clocks
Enabled
and after another ADS# signal has arrived.
Disabled
The CPU cycle is deferred immediately after receiving another ADS# signal.
DRAM Page Closing Policy
The settings are Closed or Open. If set to Closed, DRAM pages tend to be
closed after use. If set to Open, DRAM pages tend to be left open.
CD Hole
If set to Enabled, access to the address range 000DC000h - 000DFFFFh is
controlled by bits 3-2 of the PAM register. If set to Disabled, all request for
access to this address range are forwarded to the hub link.
Memory Hole
This option specifies the location of an area of memory that cannot be
addressed on the ISA bus. The settings are Disabled, 512KB-640KB, or 15MB-
16MB.
DRAM Refresh Rate
This option specifies the interval between refresh signals to DRAM system
memory. The settings are 15.6 us (microseconds), 7.9 us, or FR 128 CLKs.
DRAM Cycle Time
This optional specifies the length of the DRAM cycle time in SCLKs. The
settings are 7 SCLKs or 8 SCLKs.
Addr Setup Time
This option specifies the address set up time in SCLKs. If set to Enabled, a
new address is set up in the same clock cycle that asserts CS#. If set to
Disabled, CS# is asserted in the clock cycle after the address was issued.
CAS# Latency
This option specifies the number of SCLKs between the time when the Read
command is sampled by DRAM and the Whitney Sample reads data from
SDRAM. The settings are 3(SCLKs) or 2.
RAS# to CAS# Delay
This option specifies the length of the delay inserted between the RAS and
CAS signals of the DRAM system memory access cycle if SDRAM is installed.
S2054 Tomcat i810
Description
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