Integra DTR-7.7 Service Manual page 77

QQ
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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -9
Q211: MX26LV040 (4M-bit CMOS Single Voltage 3V High Speed Flash Memory)
BLOCK DIAGRAM
#CE
#OE
#WE
A0-A18
TE
L 13942296513
PIN CONFIGURATION
1
A11
2
A9
3
A8
4
A13
5
A14
6
A17
7
WE#
VCC 8
A18 9
10
A16
www
11
A15
12
A12
A7 13
A6 14
A5 15 .
A4 16
http://www.xiaoyu163.com
CONTROL PROGRAM/ERASE
INPUT HIGH VOLTAGE
LOGIC
MX29LV040
FLASH
ARRAY
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
SENSE
AMPLIFIER
I/O BUFFER
Q0-Q7
32
31
30
29
28
27
26
25
MX26LV040
24
23
22
21
x ao u163
y
20
19
i 18
17
http://www.xiaoyu163.com
2 9
8
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
PGM
Q Q
3 6 7 1 3 1 5
DATA
COMMAND
HV
DATA LATCH
PROGRAM
DATA LATCH
TERMINAL DESCRIPTION
OE#
Pin Name
A10
CE#
A0~A18
Q7
Q6
Q0~Q7
Q5
Q4
CE#
Q3
GND
WE#
Q2
Q1
OE#
Q0
co
A0
GND
A1
A2 .
VCC
A3
9 4 2 8
0 5 8 2 9 9 4 2 8
Description
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
m
Output Enable Input
Ground Pin
+3.0V single power supply
DTR-7.7
9 9
9 9