Integra DTR-7.7 Service Manual page 120

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MICROPROCESSOR TERMINAL DESCRIPTIONS -1
Q701: M30627FJPGP
Pin Name
No.
1 Vref
2 AVcc
3 P97/~ADTRG/SIN4
4 P96/ANEX1/SOUT4
5 P95/ANEX0/CLK4
6 P94/DA1/TB4IN
7 P93/DA0/TB3IN
8 P92/TB2IN/SOUT3
9 P91/TB1IN/SIN3
10 P90/TB0IN/CLK3
11 P141
12 P140
13 BYTE
14 CNVSS
15 P87/XCIN
16 P86/XCOUT
17 ~RESET
18 XOUT
19 VSS
20 XIN
21 VCC1
22 P85/~NMI
23 P84/~INT2
24 P83/~INT1
25 P82/~INT0
26 P81/TA4IN/~U
27 P80/TA4OUT/U
28 P77/TA3IN
29 P76/TA3OUT
30 P75/TA2IN/~W
TE
L 13942296513
31 P74/TA2OUT/W
32 P73/~CTS2/~RTS2/TA1IN/~V
33 P72/CLK2/TA1OUT/V
34 P71/RXD2/SCL2/TA0IN/TB5IN
35 P70/TXD2/SDA2/TA0OUT
36 P67/TXD1/SDA1
37 Vcc1
38 P66/RXD1/SCL1
39 Vss
40 P65/CLK1
41
P64/~CTS1/~RTS1/~CTS0/CLKS1
42 P63/TXD0/SDA0
43 P62/RXD0/SCL0
44 P61/CLK0
45 P60/~CTS0/~RTS0
46 P137
47 P136
48 P135
49 P134
50 P57/~RDY/CLKOUT
51 P56/ALE
52 P55/~HOLD
53 P54/~HLDA
54 P133
55 P132
56 P131
57 P130
58 P53/BCLK
59 P52/~RD
60 P51/~WRH/~BHE
61 P50/~WRL/~WR
www
62 P127
63 P126
64 P125
.
http://www.xiaoyu163.com
Function
I/O
Vref ---
---
AVcc
I
VMSDI
O
VMSDO
O
VMCLK
VCRST O
O
~VMUT
OSDSDO O
SYNC I
OSDCLK O
O
~OSDCS
---
O
---
BYTE
---
CNVss
RDSDATA I
O
XMSRSEL
~RESET I
---
Xout
---
Vss
---
Xin
---
Vcc1
~NMI I
POFF I
VSYNC I
I
~XMERRIRQ/~RDSCLK
XMCOMSEL O
~XMDACRST O
~DIRINT0 I
DSPFCS O
DSPBUSY I
I
~DSPINT
~DSPFINT I
I
~SDET
PLLSCL O
PLLSDA I/O
FTXD O
---
---
FRXD I
---
---
FCLK O
FBUSY O
XMSRTXD O
XMSRRXD I
~XMRST O
~DIRCS
O
OSDINV O
OSDINY O
---
O
---
O
~DIRRST O
~DSPCS O
~FEPM O
~DSPRST O
--- O
---
O
MCHSEL O
~ADCRST O
DIGCLK O
DIGSDI I
DIGSDO O
I
~FCE
--- O
Z2MUT O
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SBZ2MUT O
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http://www.xiaoyu163.com
2 9
8
Act.
---
A/D Reference Voltage
---
A/D Power supply
H
Data input pin from HDMI micro prosessor
Data output pin to HDMI micro prosessor
H
CLK Clock output pin to HDMI micro prosessor
H Reset cotrol pin to Video Encoder/Decoder
L
VIDEO MUTE control pin
H Data output pin to OSD
H
VIDEO SYNC detect pin
Clock output pin to OSD
CLK
L
OSD chip select pin
H
No use
---
External bus width select pin. Connect to Ground.
---
Processor mode select pin. Connect to the ground via resistor.
H RDS data input from LA72725 in tuner pack
H XM/SIRIUS select pin
L
Reset input
--- Ceramic oscillator connection pin.
---
Power supply Ground pin
---
Ceramic oscillator connection pin.
---
Power supply pin
L No use
L Power failure detection input
L
Vertical sync signal detection input.
L (D-type)XM IC interrupt input / (P-type)RDS clock input / (Other type)No use
H
Control output to XM IC
XM DAC reset pin
L
H DIR/Codec unlock detect pin
DSP AB chip select pin
L
Q Q
H DSP C BUSY detect pin
3 6 7 1 3 1 5
DSP C interrupt detect pin
L
L
DSP AB interrupt detect pin
S-VIDEO detect pin
L
I2C clock output to tuner pack
CLK
H I2C data input/output from/to tuner pack
H Flash micro processor rewrite port
H
Power supply
H
Flash micro processor rewrite port
H Power supply Ground
Flash micro processor rewrite port
CLK
H
Flash micro processor rewrite port
H XM/SIRIUS data output pin
H
XM/SIRIUS data input pin
L XM IC reset pin
L
DIR/Codec chip select pin
H OSD IC input select pin(Video)
H
OSD IC input select pin(S Video)
H No use
H No use
DIR/Codec reset control pin
L
L
DSP chip select pin
H
Flash micro processor rewrite port
L DSP reset pin
H No use
H No use
H
ANALOG/HDMI MCLK select pin
Mult-ch AD Reset output
L
CLK DIR/Codec/DSP clock output pin
H DIR/Codec/DSP data input pin
H
DIR/Codec/DSP data output pin
H Flash micro processor rewrite port
No use
H
Mute output for ZONE2
H
co
H Mute output for SB/ZONE2
.
9 4 2 8
Description
0 5 8 2 9 9 4 2 8
m
DTR-7.7
9 9
9 9