Integra DTR-7.7 Service Manual page 105

QQ
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IC BLOCK DI AGRAMS AND TERMINAL DESCRIPTIONS -37
Q8101: ADV7401 (Multi-Format SDTV/HDTV Video Decoder)
TERMINAL DESCRIPTION (2/3)
Pin No.
33, 32, 31,
30, 29, 24,
14, 13
44, 43, 21,
20, 45, 34,
2, 1, 100,
97, 96, 95,
88, 87, 84,
83
3
4
99
98
81, 19
TE
L 13942296513
82, 16
80
78
36
38
37
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46
.
70
59
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Mnemonic Type
P22-P29 I/O
P0–P1, P10– I
P11, P20–P21,
P31–P40
INT O
HS/CS O
VS O
FIELD/DE O
SDA1, SDA2 I/O
SCLK1, I
SCLK2
ALSB I
RESET I
LLC1 O
XTAL I
XTAL1 O
x ao
ELPF O
y
i
TEST0
TEST1 O
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8
Function
Video input/output port
Video pixel input port.
Interrupt pin, can be active low or active high. When SDP/CP
status bits change this pin will trigger. The set of events which
will trigger an interrupt are under user control.
HS is a horizontal synchronization output signal in SDP and
CP modes. CS is a digital composite synchronization signal
that can be selected while in CP mode.
VS is a vertical synchronization output signal in SDP and CP
modes.
FIELD is a field synchronization output signal in all
interlaced video modes. This pin also can be enabled as a DE
(Data Enable) signal in CP mode to allow direct connection to
a HDMI/DVI Tx IC.
2
Q Q
I C port serial data input/output pin, SDA1 is the data line for
3 6 7 1 3
the Control port and SDA2 is the data line for the VBI
readback port.
2
I C port serial clock input (max clock rate of 400 kHz).
SCLK1 is the clock line for the Control port and SCLK2 is
the clock line for the VBI data readback port.
2
This pin selects the I C address for the ADV7401 Control and
VBI readback ports. ALSB set to a logic 0 sets the address for
a write to control port of 0x40 and the readback address for
the VBI port of 0x21. ALSB set to a logic high sets the
address for a write to control port of 0x42 and the readback
address for the VBI port of 0x23.
System reset input, active low. A minimum low reset pulse
width of 5 ms is required to reset the ADV7401 circuitry.
LLC1 is a line locked output clock for the pixel data (range is
12.825MHz to 140MHz for ADV7401KSTZ-140;
12.825MHz to 110MHz for ADV7401BSTZ-110;
12.825MHz to 80MHz for ADV7401BSTZ-80).
Input pin for 28.63636 MHz crystal, or can be overdriven by
an external 3.3 V 28.63636 MHz clock oscillator source to
clock the ADV7401.
This pin should be connected to the 28.63636 MHz crystal or
left as a no connect if an external 3.3 V 28.63636 MHz clock
oscillator source is used to clock the ADV7401. In crystal
mode the crystal must be a fundamental crystal.
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The recommend external loop filter must be connected to this
ELPF pin.
.
These pins should be left unconnected or alternatively tie to
AGND
These pins should be left unconnected
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
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DTR-7.7
9 9
2 8 9 9