Integra DTR-7.7 Service Manual page 106

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IC BLOCK DI AGRAMS AND TERMINAL DESCRIPTIONS -38
Q8101: ADV7401 (Multi-Format SDTV/HDTV Video Decoder)
TERMINAL DESCRIPTION (3/3)
Pin No. Mnemonic
15 SFL/SYNC_ O
64
65
61, 62
68, 69
67
86
85
79
TE
L 13942296513
35
52
77
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Type
O
UT
REFOUT O
CML O
CAPY1– I
CAPY2
CAPC1– I
CAPC2
BIAS O
HS_IN/CS_IN I
VS_IN I
DE_IN I
DCLK_IN I
SOG I
SOY I
x ao
y
i
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Function
SFL (Subcarrier Frequency Lock); this pin contains a serial
output stream which can be used to lock the subcarrier
frequency when this decoder is connected to any Analog
Devices digital video encoder. SYNC_OUT is the sliced sync
output signal only available in CP mode.
Internal voltage reference output.
The CML pin is a common-mode level for the internal ADCs.
ADC capacitor network.
ADC capacitor network.
BIAS is an external bias setting pin. Connect the
recommended resistor (1.35k ) between pin and ground.
Can be configured in CP mode to be either a digital HS input
signal or a digital CS input signal used to extract timing in a
5-wire or 4-wire RGB mode.
VS input signal used in CP mode for 5-wire timing mode.
DE_IN is a data enable input signal used in 24-bit digital
input port mode, for example,
Q Q
24-bit RGB data from a DVI Rx IC.
3 6 7 1 3
DCLK_IN is a clock input signal used in 24-bit digital input
mode (e.g. 24-bit RGB data from a DVI Rx IC) and also in
digital CVBS input mode.
SOG is a sync on green input used in embedded sync mode.
SOY is a sync on luma input used in embedded sync mode.
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DTR-7.7
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