Samsung WA31273A Technical Manual page 92

AT INTERFACE and ATA COMMANDS
6-7 Timing
6-7-1 ATA Host Interface Timing Parameters
ATA Host Interface Timing parameters are shown in Table 6-12.
Table 6-12. ATA Host Interface Timing Parameters
Symbol
TPW
TRDA
TWDS
TWDH
TRDH
TADS
TADH
TIOCSL
TIOCHL
TIOCHPW
TIOCSH
THCS
THCH
TDDRQL
TDACKS
TDKA
TADV
TMACH
TDHT *
TMWC
Applies at end of an ATA multi-word DMA cycle, when DMACKB is negated
*
6-
48 WA31273A / WA32543A / WA33203A / WA3216A / WA31083A / WA32162A
PARAMETER
DIORB/DIOWB- Pulse Width
DD Drive from DIORB asserted
Write data setup time to DIOWB
Write data hold time from DIOWB
Read data hold time from DIORB
Address setup time to DIORB/ DIOWB
Address hold time from DIORB/DIOWB
Address setup time to IOCS16B
DIORB/DIOWB asserted to IORDY
IORDY- pulse width
Address hold time from IOCS16B
CS setup time from IOCS16B
CS hold time from DIORB/DIOWB
DIORB/DIOWB asserted to DMARQ
DMACKB setup time to DIORB/DIOWB
DMACKB asserted to DD valid
CS and DA valid to DD valid
DIORB/DIOWB hold time to DMACKB
DMACKB negated to DD tristated
Multi-word DMA cycle time
TIMING
MIN TYP MAX
10
25
5
5
20 70
5
10
15
20
25
14
10
10
40
0
28
25
5
120
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns