Samsung WA31273A Technical Manual page 47

Winner 3a; winner 2a series ide drives
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6-2-3-6
DIOR- (Drive I/O Read)
This is the Read strobe signal. The falling edge of DIOR- enables data from a register or
the data port of the drive onto the host data bus, DD0-DD7 or DD0-DD15. The rising
edge of DIOR- latches data at the host.
6-2-3-7
DIOW- (Drive I/O Write)
This is the Write strobe signal. The rising edge of DIOW- clocks data from the host data
bus, DD0-DD7 or DD0- DD15, into a register or the data port of the drive.
6-2-3-8
DMACK- (DMA Acknowledge)
This signal shall be used by the host in response to DMARQ to either acknowledge that
data has been accepted, or that data is available.
6-2-3-9
DMARQ (DMA Request)
This signal, used for DMA data transfers between host and drive, shall be asserted by
the drive when it is ready to transfer data to or from the host. The direction of data
transfer is controlled by DIOR- and DIOW-. The signal is used in handshake manner
with DMACK- (i.e. the drive shall wait until the host asserts DMACK- before negating
DMARQ, and re-asserting DMARQ if there is more data to transfer).
When a DMA operation is enabled, IOCS16-, CSIFX- shall not be asserted and transfers
shall be 16-bits wide.
6-2-3-10
INTRQ (Drive Interrupt)
This signal is used to interrupt the host system. INTRQ is asserted only when the drive
has a pending interrupt, the drive is selected, and the host has cleared nIEN in the
Device Control Register. If nIEN=1, or the drive is not selected, this output is in a high
impedance state, regardless of the presence or absence of a pending interrupt.
INTRQ is negated by:
• assertion of RESET- or
• the setting of SRST of the Device Control Register or
• the host writing to the Command Register or
• the host reading from the Status Register
On PIO transfers, INTRQ is asserted at the beginning of each data block to be
transferred. A data block is typically a single sector, except when declared otherwise by
use of the Set Multiple command. An exception occurs on Format Track, Write Sector(s),
Write Buffer and Write Long commands - INTRQ shall not be asserted at the beginning
of the first data block to be transferred.
WA31273A / WA32543A / WA33203A / WA32163A / WA31083A / WA32162A 6-3
AT INTERFACE and ATA COMMANDS

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