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DDR3 and DDR4 JEDEC Timing Violations Summary
5.1.29 V30 - tPRPDEN PRECHARGE / PRECHARGE ALL to POWER DOWN ENTRY
Defined as the minimum interval between Precharge/PreCharge All to Power Down Entry.
The minimum interval before PDE is asserted 1 nCK.
5.1.30 V31 - tRDPDEN READ / READ AUTO to POWER DOWN ENTRY
Defined as the minimum interval between Read / Read Auto and initiating Power Down
Entry (PDE). This is calculated as RL (AL + CL) + (BC4)?2:4 + 1CK for all speed bins.
5.1.31 V32 - tWRPDEN WRITE to POWER DOWN ENTRY
Defined as the minimum interval between Write command and initiating Power down
entry. This is calculated as WL (AL + CWL) + (BC4)?2:4 + (tWR / tCK(avg) +1 CK) for all
speed bins.
5.1.32 V33 - tWRAPDEN WRITE AUTO to POWER DOWN ENTRY
Defined as the minimum interval between Write with Auto command and initiating
Power down entry. This is calculated as WL (AL + CWL) + (BC4)?2:4 + WR + 1CK for all
speed bins (where WR (CKs) as programmed in MR0).
5.1.33 V34 - tXP POWER DOWN EXIT to a Valid Command without DLL
Defined as the minimum interval between initiating Power Down Exit and the next Valid
Command that doesn't need DLL. "Without DLL" indicates DLL was not disabled during
Power Down and a fast exit of Power Down is being used. This is calculated as:
Speed
Grade
Min
(CKs)
5.1.34 V35 - tXPDLL POWER DOWN EXIT to a Valid Command with DLL - DDR3
Defined as the minimum interval between initiating Power Down Exit and the next Valid
Command that needs DLL. With DLL enabled after Power Down it takes longer to lock to
the clock signal. Slow exit from power down is used and requires more clock times for the
DLL to lock before the first valid command can be issued. This is calculated as
Max(10nCK,24 ns) for all speed bins.
K ibra DDR Protocol Analyzer User Manual
800
1066
Max(3nCK, 7.5 ns) Max(3nCK, 7.5 ns) Max(3nCK, 6 ns)
1333
1600
Max(3nCK, 6 ns)
T eledyne LeCroy
161
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